`timescale 1ns / 10ps
module IF_Stage(
  input         clock,
  input         reset,
  input         io_pc_ena,
  input  [63:0] io_pc_in,
  output [63:0] io_pc_out,
  output [63:0] io_inst_addr,
  output        io_inst_ena
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] pc; // @[IF_Stage.scala 17:42]
  reg [63:0] the_addr; // @[IF_Stage.scala 18:34]
  wire [63:0] _pc_T_1 = io_pc_in + 64'h4; // @[IF_Stage.scala 30:61]
  wire [63:0] _pc_T_3 = pc + 64'h4; // @[IF_Stage.scala 34:55]
  assign io_pc_out = reset ? 64'h0 : the_addr; // @[IF_Stage.scala 20:23 IF_Stage.scala 26:33 IF_Stage.scala 39:33]
  assign io_inst_addr = the_addr; // @[IF_Stage.scala 41:33]
  assign io_inst_ena = reset ? 1'h0 : 1'h1; // @[IF_Stage.scala 20:23 IF_Stage.scala 24:33 IF_Stage.scala 38:33]
  always @(posedge clock) begin
    if (reset) begin // @[IF_Stage.scala 17:42]
      pc <= 64'h0; // @[IF_Stage.scala 17:42]
    end else if (reset) begin // @[IF_Stage.scala 20:23]
      pc <= 64'h0; // @[IF_Stage.scala 21:33]
    end else if (io_pc_ena) begin // @[IF_Stage.scala 29:41]
      pc <= _pc_T_1; // @[IF_Stage.scala 30:49]
    end else begin
      pc <= _pc_T_3; // @[IF_Stage.scala 34:49]
    end
    if (reset) begin // @[IF_Stage.scala 18:34]
      the_addr <= 64'h0; // @[IF_Stage.scala 18:34]
    end else if (reset) begin // @[IF_Stage.scala 20:23]
      the_addr <= 64'h0; // @[IF_Stage.scala 22:41]
    end else if (io_pc_ena) begin // @[IF_Stage.scala 29:41]
      the_addr <= io_pc_in; // @[IF_Stage.scala 31:41]
    end else begin
      the_addr <= pc; // @[IF_Stage.scala 35:41]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  pc = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  the_addr = _RAND_1[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ID_Stage(
  input         clock,
  input         reset,
  input  [31:0] io_inst,
  input  [63:0] io_rs1_data,
  input  [63:0] io_rs2_data,
  input  [63:0] io_pc_out,
  output        io_rs1_r_ena,
  output [4:0]  io_rs1_r_addr,
  output        io_rs2_r_ena,
  output [4:0]  io_rs2_r_addr,
  output        io_rd_w_ena,
  output [4:0]  io_rd_w_addr,
  output [4:0]  io_inst_type,
  output [7:0]  io_inst_opcode,
  output [63:0] io_op1,
  output [63:0] io_op2,
  output        io_pc_ena_j,
  output        io_pc_ena_b,
  output [63:0] io_offset,
  output [1:0]  io_mem_sel,
  output        io_mem_ext
);
  wire [6:0] opcode = io_inst[6:0]; // @[ID_Stage.scala 40:30]
  wire [4:0] rd = io_inst[11:7]; // @[ID_Stage.scala 41:30]
  wire [2:0] func3 = io_inst[14:12]; // @[ID_Stage.scala 42:30]
  wire [4:0] rs1 = io_inst[19:15]; // @[ID_Stage.scala 43:30]
  wire [4:0] rs2 = io_inst[24:20]; // @[ID_Stage.scala 44:30]
  wire  _T_2 = opcode[6:2] == 5'h4; // @[ID_Stage.scala 101:27]
  wire  _T_3 = func3 == 3'h0; // @[ID_Stage.scala 108:42]
  wire [11:0] imm = reset ? io_inst[31:20] : io_inst[31:20]; // @[ID_Stage.scala 52:24 ID_Stage.scala 75:25 ID_Stage.scala 98:25]
  wire [5:0] op2_mul_lo_lo_lo = {imm[11],imm[11],imm[11],imm[11],imm[11],imm[11]}; // @[ID_Stage.scala 108:140]
  wire [12:0] op2_mul_lo_lo = {imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],op2_mul_lo_lo_lo}; // @[ID_Stage.scala 108:140]
  wire [25:0] op2_mul_lo = {imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],op2_mul_lo_lo_lo,op2_mul_lo_lo}; // @[ID_Stage.scala 108:140]
  wire [51:0] op2_mul_hi_1 = {imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],imm[11],op2_mul_lo_lo_lo,op2_mul_lo_lo,
    op2_mul_lo}; // @[ID_Stage.scala 108:140]
  wire [63:0] _op2_mul_T_52 = {op2_mul_hi_1,imm}; // @[Cat.scala 30:58]
  wire  _T_4 = func3 == 3'h2; // @[ID_Stage.scala 109:42]
  wire  _T_5 = func3 == 3'h3; // @[ID_Stage.scala 110:42]
  wire  _T_6 = func3 == 3'h7; // @[ID_Stage.scala 111:42]
  wire  _T_7 = func3 == 3'h6; // @[ID_Stage.scala 112:42]
  wire  _T_8 = func3 == 3'h4; // @[ID_Stage.scala 113:42]
  wire  _T_9 = func3 == 3'h1; // @[ID_Stage.scala 114:42]
  wire [5:0] op2_mul_lo_7 = io_inst[25:20]; // @[ID_Stage.scala 114:156]
  wire [63:0] _op2_mul_T_318 = {58'h0,op2_mul_lo_7}; // @[Cat.scala 30:58]
  wire  _T_10 = func3 == 3'h5; // @[ID_Stage.scala 115:42]
  wire [4:0] _GEN_0 = imm[10] ? 5'h13 : 5'h14; // @[ID_Stage.scala 116:65 ID_Stage.scala 116:82 ID_Stage.scala 117:78]
  wire [63:0] _GEN_1 = imm[10] ? _op2_mul_T_318 : _op2_mul_T_318; // @[ID_Stage.scala 116:65 ID_Stage.scala 116:103 ID_Stage.scala 117:99]
  wire [4:0] _GEN_2 = func3 == 3'h5 ? _GEN_0 : 5'h0; // @[ID_Stage.scala 115:57 ID_Stage.scala 119:74]
  wire [63:0] _GEN_3 = func3 == 3'h5 ? _GEN_1 : 64'h0; // @[ID_Stage.scala 115:57 ID_Stage.scala 119:99]
  wire [4:0] _GEN_4 = func3 == 3'h1 ? 5'h12 : _GEN_2; // @[ID_Stage.scala 114:57 ID_Stage.scala 114:74]
  wire [63:0] _GEN_5 = func3 == 3'h1 ? _op2_mul_T_318 : _GEN_3; // @[ID_Stage.scala 114:57 ID_Stage.scala 114:95]
  wire [4:0] _GEN_6 = func3 == 3'h4 ? 5'h19 : _GEN_4; // @[ID_Stage.scala 113:57 ID_Stage.scala 113:74]
  wire [63:0] _GEN_7 = func3 == 3'h4 ? _op2_mul_T_52 : _GEN_5; // @[ID_Stage.scala 113:57 ID_Stage.scala 113:99]
  wire [4:0] _GEN_8 = func3 == 3'h6 ? 5'h18 : _GEN_6; // @[ID_Stage.scala 112:57 ID_Stage.scala 112:74]
  wire [63:0] _GEN_9 = func3 == 3'h6 ? _op2_mul_T_52 : _GEN_7; // @[ID_Stage.scala 112:57 ID_Stage.scala 112:99]
  wire [4:0] _GEN_10 = func3 == 3'h7 ? 5'h17 : _GEN_8; // @[ID_Stage.scala 111:57 ID_Stage.scala 111:74]
  wire [63:0] _GEN_11 = func3 == 3'h7 ? _op2_mul_T_52 : _GEN_9; // @[ID_Stage.scala 111:57 ID_Stage.scala 111:99]
  wire [4:0] _GEN_12 = func3 == 3'h3 ? 5'h16 : _GEN_10; // @[ID_Stage.scala 110:57 ID_Stage.scala 110:74]
  wire [63:0] _GEN_13 = func3 == 3'h3 ? _op2_mul_T_52 : _GEN_11; // @[ID_Stage.scala 110:57 ID_Stage.scala 110:95]
  wire [4:0] _GEN_14 = func3 == 3'h2 ? 5'h15 : _GEN_12; // @[ID_Stage.scala 109:57 ID_Stage.scala 109:74]
  wire [63:0] _GEN_15 = func3 == 3'h2 ? _op2_mul_T_52 : _GEN_13; // @[ID_Stage.scala 109:57 ID_Stage.scala 109:99]
  wire [4:0] _GEN_16 = func3 == 3'h0 ? 5'h11 : _GEN_14; // @[ID_Stage.scala 108:57 ID_Stage.scala 108:74]
  wire [63:0] _GEN_17 = func3 == 3'h0 ? _op2_mul_T_52 : _GEN_15; // @[ID_Stage.scala 108:57 ID_Stage.scala 108:99]
  wire  _T_14 = opcode[6:2] == 5'h6; // @[ID_Stage.scala 122:40]
  wire [31:0] op1_mul_lo_1 = io_rs1_data[31:0]; // @[ID_Stage.scala 125:106]
  wire [63:0] _op1_mul_T = {32'h0,op1_mul_lo_1}; // @[Cat.scala 30:58]
  wire [63:0] _op2_mul_T_374 = {59'h0,rs2}; // @[Cat.scala 30:58]
  wire [5:0] _GEN_18 = imm[10] ? 6'h23 : 6'h22; // @[ID_Stage.scala 133:65 ID_Stage.scala 133:82 ID_Stage.scala 134:78]
  wire [63:0] _GEN_19 = imm[10] ? _op2_mul_T_374 : _op2_mul_T_374; // @[ID_Stage.scala 133:65 ID_Stage.scala 133:103 ID_Stage.scala 134:99]
  wire [5:0] _GEN_20 = _T_10 ? _GEN_18 : 6'h0; // @[ID_Stage.scala 132:57 ID_Stage.scala 136:74]
  wire [63:0] _GEN_21 = _T_10 ? _GEN_19 : _op2_mul_T_52; // @[ID_Stage.scala 132:57 ID_Stage.scala 126:49]
  wire [5:0] _GEN_22 = _T_9 ? 6'h21 : _GEN_20; // @[ID_Stage.scala 131:57 ID_Stage.scala 131:74]
  wire [63:0] _GEN_23 = _T_9 ? _op2_mul_T_374 : _GEN_21; // @[ID_Stage.scala 131:57 ID_Stage.scala 131:95]
  wire [5:0] _GEN_24 = _T_3 ? 6'h1f : _GEN_22; // @[ID_Stage.scala 130:57 ID_Stage.scala 130:74]
  wire [63:0] _GEN_25 = _T_3 ? _op2_mul_T_52 : _GEN_23; // @[ID_Stage.scala 130:57 ID_Stage.scala 126:49]
  wire  _T_21 = opcode[6:2] == 5'hd; // @[ID_Stage.scala 139:40]
  wire  _T_23 = opcode[6:2] == 5'h5; // @[ID_Stage.scala 149:40]
  wire [31:0] _GEN_226 = {io_inst[31:12], 12'h0}; // @[ID_Stage.scala 155:96]
  wire [34:0] _op2_mul_T_378 = {{3'd0}, _GEN_226}; // @[ID_Stage.scala 155:96]
  wire [7:0] op2_mul_lo_lo_13 = {_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],
    _op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31]}; // @[ID_Stage.scala 155:112]
  wire [15:0] op2_mul_lo_16 = {_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],
    _op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],op2_mul_lo_lo_13}; // @[ID_Stage.scala 155:112]
  wire [31:0] op2_mul_hi_27 = {_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],
    _op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],_op2_mul_T_378[31],op2_mul_lo_lo_13,op2_mul_lo_16}; // @[ID_Stage.scala 155:112]
  wire [31:0] op2_mul_lo_17 = _op2_mul_T_378[31:0]; // @[ID_Stage.scala 155:155]
  wire [63:0] _op2_mul_T_475 = {op2_mul_hi_27,op2_mul_lo_17}; // @[Cat.scala 30:58]
  wire  _T_25 = opcode[6:2] == 5'hc; // @[ID_Stage.scala 160:32]
  wire [4:0] _GEN_26 = imm[10] ? 5'h1a : 5'h11; // @[ID_Stage.scala 169:65 ID_Stage.scala 169:82 ID_Stage.scala 170:78]
  wire [5:0] _GEN_28 = imm[10] ? io_rs2_data[5:0] : io_rs2_data[5:0]; // @[ID_Stage.scala 179:65 ID_Stage.scala 179:102 ID_Stage.scala 180:98]
  wire [63:0] _GEN_30 = _T_10 ? {{58'd0}, _GEN_28} : io_rs2_data; // @[ID_Stage.scala 178:57 ID_Stage.scala 164:49]
  wire [63:0] _GEN_32 = _T_9 ? {{58'd0}, io_rs2_data[5:0]} : _GEN_30; // @[ID_Stage.scala 177:57 ID_Stage.scala 177:94]
  wire [63:0] _GEN_34 = _T_8 ? io_rs2_data : _GEN_32; // @[ID_Stage.scala 176:57 ID_Stage.scala 164:49]
  wire [63:0] _GEN_36 = _T_7 ? io_rs2_data : _GEN_34; // @[ID_Stage.scala 175:57 ID_Stage.scala 164:49]
  wire [63:0] _GEN_38 = _T_6 ? io_rs2_data : _GEN_36; // @[ID_Stage.scala 174:57 ID_Stage.scala 164:49]
  wire [63:0] _GEN_40 = _T_5 ? io_rs2_data : _GEN_38; // @[ID_Stage.scala 173:57 ID_Stage.scala 164:49]
  wire [63:0] _GEN_42 = _T_4 ? io_rs2_data : _GEN_40; // @[ID_Stage.scala 172:57 ID_Stage.scala 164:49]
  wire [4:0] _GEN_43 = _T_3 ? _GEN_26 : _GEN_14; // @[ID_Stage.scala 168:65]
  wire [63:0] _GEN_44 = _T_3 ? io_rs2_data : _GEN_42; // @[ID_Stage.scala 168:65 ID_Stage.scala 164:49]
  wire  _T_39 = opcode[6:2] == 5'he; // @[ID_Stage.scala 185:40]
  wire [5:0] _GEN_45 = imm[10] ? 6'h20 : 6'h1f; // @[ID_Stage.scala 193:65 ID_Stage.scala 193:82 ID_Stage.scala 194:78]
  wire [5:0] _GEN_49 = _T_3 ? _GEN_45 : _GEN_22; // @[ID_Stage.scala 192:65]
  wire  _T_48 = opcode[6:2] == 5'h1b; // @[ID_Stage.scala 204:32]
  wire [4:0] op2_mul_lo_lo_lo_14 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31]}; // @[ID_Stage.scala 210:94]
  wire [5:0] op2_mul_lo_lo_hi_14 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31]}; // @[ID_Stage.scala 210:94]
  wire [10:0] op2_mul_lo_lo_14 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_lo_14}; // @[ID_Stage.scala 210:94]
  wire [21:0] op2_mul_lo_18 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_lo_14,op2_mul_lo_lo_14}; // @[ID_Stage.scala 210:94]
  wire [7:0] op2_mul_hi_hi_lo_15 = io_inst[19:12]; // @[ID_Stage.scala 210:110]
  wire  op2_mul_hi_lo_15 = io_inst[20]; // @[ID_Stage.scala 210:126]
  wire [9:0] op2_mul_lo_hi_15 = io_inst[30:21]; // @[ID_Stage.scala 210:139]
  wire [51:0] op2_mul_hi_hi_15 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_lo_14,op2_mul_lo_lo_14,op2_mul_lo_18,op2_mul_hi_hi_lo_15}; // @[Cat.scala 30:58]
  wire [63:0] _op2_mul_T_523 = {op2_mul_hi_hi_15,op2_mul_hi_lo_15,op2_mul_lo_hi_15,1'h0}; // @[Cat.scala 30:58]
  wire  _T_50 = opcode[6:2] == 5'h19; // @[ID_Stage.scala 215:32]
  wire  _T_52 = opcode[6:2] == 5'h18; // @[ID_Stage.scala 226:40]
  wire [11:0] io_offset_lo_lo = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_hi_14}; // @[ID_Stage.scala 229:94]
  wire [12:0] io_offset_lo_hi = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_hi_14}; // @[ID_Stage.scala 229:94]
  wire [24:0] io_offset_lo = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_hi_14,io_offset_lo_lo}; // @[ID_Stage.scala 229:94]
  wire [25:0] io_offset_hi = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_hi_14,io_offset_lo_hi}; // @[ID_Stage.scala 229:94]
  wire [50:0] io_offset_hi_hi_hi_1 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31
    ],op2_mul_lo_lo_hi_14,io_offset_lo_hi,io_offset_lo}; // @[ID_Stage.scala 229:94]
  wire  io_offset_hi_lo_1 = rd[0]; // @[ID_Stage.scala 229:118]
  wire [5:0] io_offset_lo_hi_hi_1 = io_inst[30:25]; // @[ID_Stage.scala 229:130]
  wire [3:0] io_offset_lo_hi_lo_1 = rd[4:1]; // @[ID_Stage.scala 229:141]
  wire [63:0] _io_offset_T_51 = {io_offset_hi_hi_hi_1,io_inst[31],io_offset_hi_lo_1,io_offset_lo_hi_hi_1,
    io_offset_lo_hi_lo_1,1'h0}; // @[Cat.scala 30:58]
  wire [4:0] _GEN_50 = _T_6 ? 5'h1e : 5'h0; // @[ID_Stage.scala 241:65 ID_Stage.scala 241:82 ID_Stage.scala 242:106]
  wire [4:0] _GEN_51 = _T_10 ? 5'h1d : _GEN_50; // @[ID_Stage.scala 240:65 ID_Stage.scala 240:82]
  wire [4:0] _GEN_52 = _T_7 ? 5'h16 : _GEN_51; // @[ID_Stage.scala 239:65 ID_Stage.scala 239:82]
  wire [4:0] _GEN_53 = _T_8 ? 5'h15 : _GEN_52; // @[ID_Stage.scala 238:65 ID_Stage.scala 238:82]
  wire [4:0] _GEN_54 = _T_9 ? 5'h1c : _GEN_53; // @[ID_Stage.scala 237:65 ID_Stage.scala 237:82]
  wire [4:0] _GEN_55 = _T_3 ? 5'h1b : _GEN_54; // @[ID_Stage.scala 236:65 ID_Stage.scala 236:82]
  wire  _T_60 = opcode[6:2] == 5'h0; // @[ID_Stage.scala 246:32]
  wire [4:0] _GEN_56 = _T_7 ? 5'h11 : 5'h0; // @[ID_Stage.scala 260:57 ID_Stage.scala 260:74 ID_Stage.scala 261:74]
  wire [1:0] _GEN_57 = _T_7 ? 2'h2 : 2'h0; // @[ID_Stage.scala 260:57 ID_Stage.scala 260:97 ID_Stage.scala 261:97]
  wire [4:0] _GEN_59 = _T_5 ? 5'h11 : _GEN_56; // @[ID_Stage.scala 259:57 ID_Stage.scala 259:74]
  wire [1:0] _GEN_60 = _T_5 ? 2'h3 : _GEN_57; // @[ID_Stage.scala 259:57 ID_Stage.scala 259:97]
  wire [4:0] _GEN_62 = _T_8 ? 5'h11 : _GEN_59; // @[ID_Stage.scala 258:57 ID_Stage.scala 258:74]
  wire [1:0] _GEN_63 = _T_8 ? 2'h0 : _GEN_60; // @[ID_Stage.scala 258:57 ID_Stage.scala 258:97]
  wire [4:0] _GEN_65 = _T_3 ? 5'h11 : _GEN_62; // @[ID_Stage.scala 257:57 ID_Stage.scala 257:74]
  wire [1:0] _GEN_66 = _T_3 ? 2'h0 : _GEN_63; // @[ID_Stage.scala 257:57 ID_Stage.scala 257:97]
  wire [4:0] _GEN_68 = _T_10 ? 5'h11 : _GEN_65; // @[ID_Stage.scala 256:57 ID_Stage.scala 256:74]
  wire [1:0] _GEN_69 = _T_10 ? 2'h1 : _GEN_66; // @[ID_Stage.scala 256:57 ID_Stage.scala 256:97]
  wire  _GEN_70 = _T_10 ? 1'h0 : _T_3; // @[ID_Stage.scala 256:57 ID_Stage.scala 256:121]
  wire [4:0] _GEN_71 = _T_9 ? 5'h11 : _GEN_68; // @[ID_Stage.scala 255:57 ID_Stage.scala 255:74]
  wire [1:0] _GEN_72 = _T_9 ? 2'h1 : _GEN_69; // @[ID_Stage.scala 255:57 ID_Stage.scala 255:97]
  wire  _GEN_73 = _T_9 | _GEN_70; // @[ID_Stage.scala 255:57 ID_Stage.scala 255:121]
  wire [4:0] _GEN_74 = _T_4 ? 5'h11 : _GEN_71; // @[ID_Stage.scala 254:57 ID_Stage.scala 254:74]
  wire [1:0] _GEN_75 = _T_4 ? 2'h2 : _GEN_72; // @[ID_Stage.scala 254:57 ID_Stage.scala 254:97]
  wire  _GEN_76 = _T_4 | _GEN_73; // @[ID_Stage.scala 254:57 ID_Stage.scala 254:121]
  wire  _T_69 = opcode[6:2] == 5'h8; // @[ID_Stage.scala 264:31]
  wire [51:0] op2_mul_hi_hi_19 = {io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],io_inst[31],
    op2_mul_lo_lo_hi_14,io_offset_lo_hi,io_offset_hi}; // @[ID_Stage.scala 268:94]
  wire [6:0] op2_mul_hi_lo_19 = io_inst[31:25]; // @[ID_Stage.scala 268:110]
  wire [63:0] _op2_mul_T_682 = {op2_mul_hi_hi_19,op2_mul_hi_lo_19,rd}; // @[Cat.scala 30:58]
  wire [4:0] _GEN_77 = _T_5 ? 5'h11 : 5'h0; // @[ID_Stage.scala 275:57 ID_Stage.scala 275:74 ID_Stage.scala 276:74]
  wire [1:0] _GEN_78 = _T_5 ? 2'h3 : 2'h0; // @[ID_Stage.scala 275:57 ID_Stage.scala 275:97 ID_Stage.scala 276:97]
  wire [4:0] _GEN_80 = _T_3 ? 5'h11 : _GEN_77; // @[ID_Stage.scala 274:57 ID_Stage.scala 274:74]
  wire [1:0] _GEN_81 = _T_3 ? 2'h0 : _GEN_78; // @[ID_Stage.scala 274:57 ID_Stage.scala 274:97]
  wire [4:0] _GEN_83 = _T_9 ? 5'h11 : _GEN_80; // @[ID_Stage.scala 273:57 ID_Stage.scala 273:74]
  wire [1:0] _GEN_84 = _T_9 ? 2'h1 : _GEN_81; // @[ID_Stage.scala 273:57 ID_Stage.scala 273:97]
  wire  _GEN_85 = _T_9 | _T_3; // @[ID_Stage.scala 273:57 ID_Stage.scala 273:121]
  wire [4:0] _GEN_86 = _T_4 ? 5'h11 : _GEN_83; // @[ID_Stage.scala 272:57 ID_Stage.scala 272:74]
  wire [1:0] _GEN_87 = _T_4 ? 2'h2 : _GEN_84; // @[ID_Stage.scala 272:57 ID_Stage.scala 272:97]
  wire  _GEN_88 = _T_4 ? 1'h0 : _GEN_85; // @[ID_Stage.scala 272:57 ID_Stage.scala 272:121]
  wire  _T_75 = opcode[6:2] == 5'h1f; // @[ID_Stage.scala 280:39]
  wire [63:0] _GEN_132 = opcode[6:2] == 5'h1b ? io_pc_out : io_rs1_data; // @[ID_Stage.scala 204:48 ID_Stage.scala 209:49]
  wire [63:0] _GEN_141 = opcode[6:2] == 5'he ? io_rs1_data : _GEN_132; // @[ID_Stage.scala 185:55 ID_Stage.scala 187:49]
  wire [63:0] _GEN_152 = opcode[6:2] == 5'hc ? io_rs1_data : _GEN_141; // @[ID_Stage.scala 160:48 ID_Stage.scala 163:49]
  wire [63:0] _GEN_164 = opcode[6:2] == 5'h5 ? io_pc_out : _GEN_152; // @[ID_Stage.scala 149:58 ID_Stage.scala 153:49]
  wire [63:0] _GEN_175 = opcode[6:2] == 5'hd ? {{44'd0}, io_inst[31:12]} : _GEN_164; // @[ID_Stage.scala 139:56 ID_Stage.scala 143:49]
  wire [63:0] _GEN_185 = opcode[6:2] == 5'h6 ? _op1_mul_T : _GEN_175; // @[ID_Stage.scala 122:55 ID_Stage.scala 125:49]
  wire [63:0] _GEN_196 = opcode[6:2] == 5'h4 ? io_rs1_data : _GEN_185; // @[ID_Stage.scala 101:42 ID_Stage.scala 104:49]
  wire [63:0] op1_mul = reset ? 64'h0 : _GEN_196; // @[ID_Stage.scala 52:24 ID_Stage.scala 76:41]
  wire [4:0] _GEN_89 = opcode[6:2] == 5'h1f ? 5'h10 : 5'h0; // @[ID_Stage.scala 280:56 ID_Stage.scala 281:38 ID_Stage.scala 294:38]
  wire [63:0] _GEN_92 = opcode[6:2] == 5'h1f ? _op2_mul_T_52 : _op2_mul_T_52; // @[ID_Stage.scala 280:56 ID_Stage.scala 285:49 ID_Stage.scala 298:49]
  wire [4:0] _GEN_93 = opcode[6:2] == 5'h8 ? 5'h19 : _GEN_89; // @[ID_Stage.scala 264:46 ID_Stage.scala 265:38]
  wire [63:0] _GEN_95 = opcode[6:2] == 5'h8 ? _op2_mul_T_682 : _GEN_92; // @[ID_Stage.scala 264:46 ID_Stage.scala 268:49]
  wire [4:0] _GEN_97 = opcode[6:2] == 5'h8 ? _GEN_86 : 5'h0; // @[ID_Stage.scala 264:46]
  wire [1:0] _GEN_98 = opcode[6:2] == 5'h8 ? _GEN_87 : 2'h0; // @[ID_Stage.scala 264:46 ID_Stage.scala 95:33]
  wire  _GEN_99 = opcode[6:2] == 5'h8 & _GEN_88; // @[ID_Stage.scala 264:46 ID_Stage.scala 96:33]
  wire [4:0] _GEN_100 = opcode[6:2] == 5'h0 ? 5'h16 : _GEN_93; // @[ID_Stage.scala 246:48 ID_Stage.scala 247:38]
  wire [63:0] _GEN_102 = opcode[6:2] == 5'h0 ? _op2_mul_T_52 : _GEN_95; // @[ID_Stage.scala 246:48 ID_Stage.scala 250:49]
  wire [4:0] _GEN_103 = opcode[6:2] == 5'h0 ? rd : 5'h0; // @[ID_Stage.scala 246:48 ID_Stage.scala 251:49]
  wire [4:0] _GEN_105 = opcode[6:2] == 5'h0 ? _GEN_74 : _GEN_97; // @[ID_Stage.scala 246:48]
  wire [1:0] _GEN_106 = opcode[6:2] == 5'h0 ? _GEN_75 : _GEN_98; // @[ID_Stage.scala 246:48]
  wire  _GEN_107 = opcode[6:2] == 5'h0 ? _GEN_76 : _GEN_99; // @[ID_Stage.scala 246:48]
  wire [4:0] _GEN_108 = opcode[6:2] == 5'h18 ? 5'h18 : _GEN_100; // @[ID_Stage.scala 226:54 ID_Stage.scala 227:41]
  wire [63:0] _GEN_110 = opcode[6:2] == 5'h18 ? _io_offset_T_51 : 64'h0; // @[ID_Stage.scala 226:54 ID_Stage.scala 229:49 ID_Stage.scala 94:33]
  wire [63:0] _GEN_112 = opcode[6:2] == 5'h18 ? io_rs2_data : _GEN_102; // @[ID_Stage.scala 226:54 ID_Stage.scala 232:49]
  wire [4:0] _GEN_113 = opcode[6:2] == 5'h18 ? 5'h0 : _GEN_103; // @[ID_Stage.scala 226:54 ID_Stage.scala 233:49]
  wire  _GEN_114 = opcode[6:2] == 5'h18 ? 1'h0 : _T_60; // @[ID_Stage.scala 226:54 ID_Stage.scala 234:49]
  wire [4:0] _GEN_115 = opcode[6:2] == 5'h18 ? _GEN_55 : _GEN_105; // @[ID_Stage.scala 226:54]
  wire [1:0] _GEN_116 = opcode[6:2] == 5'h18 ? 2'h0 : _GEN_106; // @[ID_Stage.scala 226:54 ID_Stage.scala 95:33]
  wire  _GEN_117 = opcode[6:2] == 5'h18 ? 1'h0 : _GEN_107; // @[ID_Stage.scala 226:54 ID_Stage.scala 96:33]
  wire [4:0] _GEN_118 = opcode[6:2] == 5'h19 ? 5'h14 : _GEN_108; // @[ID_Stage.scala 215:49 ID_Stage.scala 216:41]
  wire [4:0] _GEN_119 = opcode[6:2] == 5'h19 ? 5'h11 : _GEN_115; // @[ID_Stage.scala 215:49 ID_Stage.scala 217:41]
  wire [63:0] _GEN_122 = opcode[6:2] == 5'h19 ? _op2_mul_T_52 : _GEN_112; // @[ID_Stage.scala 215:49 ID_Stage.scala 221:49]
  wire [4:0] _GEN_123 = opcode[6:2] == 5'h19 ? rd : _GEN_113; // @[ID_Stage.scala 215:49 ID_Stage.scala 222:49]
  wire  _GEN_124 = opcode[6:2] == 5'h19 | _GEN_114; // @[ID_Stage.scala 215:49 ID_Stage.scala 223:49]
  wire  _GEN_125 = opcode[6:2] == 5'h19 ? 1'h0 : _T_52; // @[ID_Stage.scala 215:49 ID_Stage.scala 93:33]
  wire [63:0] _GEN_126 = opcode[6:2] == 5'h19 ? 64'h0 : _GEN_110; // @[ID_Stage.scala 215:49 ID_Stage.scala 94:33]
  wire [1:0] _GEN_127 = opcode[6:2] == 5'h19 ? 2'h0 : _GEN_116; // @[ID_Stage.scala 215:49 ID_Stage.scala 95:33]
  wire  _GEN_128 = opcode[6:2] == 5'h19 ? 1'h0 : _GEN_117; // @[ID_Stage.scala 215:49 ID_Stage.scala 96:33]
  wire [4:0] _GEN_129 = opcode[6:2] == 5'h1b ? 5'h4 : _GEN_118; // @[ID_Stage.scala 204:48 ID_Stage.scala 205:41]
  wire [4:0] _GEN_130 = opcode[6:2] == 5'h1b ? 5'h11 : _GEN_119; // @[ID_Stage.scala 204:48 ID_Stage.scala 206:41]
  wire  _GEN_131 = opcode[6:2] == 5'h1b | _T_50; // @[ID_Stage.scala 204:48 ID_Stage.scala 207:41]
  wire [63:0] _GEN_133 = opcode[6:2] == 5'h1b ? _op2_mul_T_523 : _GEN_122; // @[ID_Stage.scala 204:48 ID_Stage.scala 210:49]
  wire [4:0] _GEN_134 = opcode[6:2] == 5'h1b ? rd : _GEN_123; // @[ID_Stage.scala 204:48 ID_Stage.scala 211:49]
  wire  _GEN_135 = opcode[6:2] == 5'h1b | _GEN_124; // @[ID_Stage.scala 204:48 ID_Stage.scala 212:49]
  wire  _GEN_136 = opcode[6:2] == 5'h1b ? 1'h0 : _GEN_125; // @[ID_Stage.scala 204:48 ID_Stage.scala 93:33]
  wire [63:0] _GEN_137 = opcode[6:2] == 5'h1b ? 64'h0 : _GEN_126; // @[ID_Stage.scala 204:48 ID_Stage.scala 94:33]
  wire [1:0] _GEN_138 = opcode[6:2] == 5'h1b ? 2'h0 : _GEN_127; // @[ID_Stage.scala 204:48 ID_Stage.scala 95:33]
  wire  _GEN_139 = opcode[6:2] == 5'h1b ? 1'h0 : _GEN_128; // @[ID_Stage.scala 204:48 ID_Stage.scala 96:33]
  wire [4:0] _GEN_140 = opcode[6:2] == 5'he ? 5'h1c : _GEN_129; // @[ID_Stage.scala 185:55 ID_Stage.scala 186:41]
  wire [63:0] _GEN_142 = opcode[6:2] == 5'he ? io_rs2_data : _GEN_133; // @[ID_Stage.scala 185:55 ID_Stage.scala 188:49]
  wire [4:0] _GEN_143 = opcode[6:2] == 5'he ? rd : _GEN_134; // @[ID_Stage.scala 185:55 ID_Stage.scala 189:49]
  wire  _GEN_144 = opcode[6:2] == 5'he | _GEN_135; // @[ID_Stage.scala 185:55 ID_Stage.scala 190:49]
  wire [5:0] _GEN_145 = opcode[6:2] == 5'he ? _GEN_49 : {{1'd0}, _GEN_130}; // @[ID_Stage.scala 185:55]
  wire  _GEN_146 = opcode[6:2] == 5'he ? 1'h0 : _GEN_131; // @[ID_Stage.scala 185:55 ID_Stage.scala 92:25]
  wire  _GEN_147 = opcode[6:2] == 5'he ? 1'h0 : _GEN_136; // @[ID_Stage.scala 185:55 ID_Stage.scala 93:33]
  wire [63:0] _GEN_148 = opcode[6:2] == 5'he ? 64'h0 : _GEN_137; // @[ID_Stage.scala 185:55 ID_Stage.scala 94:33]
  wire [1:0] _GEN_149 = opcode[6:2] == 5'he ? 2'h0 : _GEN_138; // @[ID_Stage.scala 185:55 ID_Stage.scala 95:33]
  wire  _GEN_150 = opcode[6:2] == 5'he ? 1'h0 : _GEN_139; // @[ID_Stage.scala 185:55 ID_Stage.scala 96:33]
  wire [4:0] _GEN_151 = opcode[6:2] == 5'hc ? 5'h1c : _GEN_140; // @[ID_Stage.scala 160:48 ID_Stage.scala 161:41]
  wire [63:0] _GEN_153 = opcode[6:2] == 5'hc ? _GEN_44 : _GEN_142; // @[ID_Stage.scala 160:48]
  wire [4:0] _GEN_154 = opcode[6:2] == 5'hc ? rd : _GEN_143; // @[ID_Stage.scala 160:48 ID_Stage.scala 165:49]
  wire  _GEN_155 = opcode[6:2] == 5'hc | _GEN_144; // @[ID_Stage.scala 160:48 ID_Stage.scala 166:49]
  wire [5:0] _GEN_156 = opcode[6:2] == 5'hc ? {{1'd0}, _GEN_43} : _GEN_145; // @[ID_Stage.scala 160:48]
  wire  _GEN_157 = opcode[6:2] == 5'hc ? 1'h0 : _GEN_146; // @[ID_Stage.scala 160:48 ID_Stage.scala 92:25]
  wire  _GEN_158 = opcode[6:2] == 5'hc ? 1'h0 : _GEN_147; // @[ID_Stage.scala 160:48 ID_Stage.scala 93:33]
  wire [63:0] _GEN_159 = opcode[6:2] == 5'hc ? 64'h0 : _GEN_148; // @[ID_Stage.scala 160:48 ID_Stage.scala 94:33]
  wire [1:0] _GEN_160 = opcode[6:2] == 5'hc ? 2'h0 : _GEN_149; // @[ID_Stage.scala 160:48 ID_Stage.scala 95:33]
  wire  _GEN_161 = opcode[6:2] == 5'hc ? 1'h0 : _GEN_150; // @[ID_Stage.scala 160:48 ID_Stage.scala 96:33]
  wire [4:0] _GEN_162 = opcode[6:2] == 5'h5 ? 5'h4 : _GEN_151; // @[ID_Stage.scala 149:58 ID_Stage.scala 150:38]
  wire [5:0] _GEN_163 = opcode[6:2] == 5'h5 ? 6'h11 : _GEN_156; // @[ID_Stage.scala 149:58 ID_Stage.scala 151:41]
  wire [63:0] _GEN_165 = opcode[6:2] == 5'h5 ? _op2_mul_T_475 : _GEN_153; // @[ID_Stage.scala 149:58 ID_Stage.scala 155:49]
  wire [4:0] _GEN_166 = opcode[6:2] == 5'h5 ? rd : _GEN_154; // @[ID_Stage.scala 149:58 ID_Stage.scala 156:49]
  wire  _GEN_167 = opcode[6:2] == 5'h5 | _GEN_155; // @[ID_Stage.scala 149:58 ID_Stage.scala 157:49]
  wire  _GEN_168 = opcode[6:2] == 5'h5 ? 1'h0 : _GEN_157; // @[ID_Stage.scala 149:58 ID_Stage.scala 92:25]
  wire  _GEN_169 = opcode[6:2] == 5'h5 ? 1'h0 : _GEN_158; // @[ID_Stage.scala 149:58 ID_Stage.scala 93:33]
  wire [63:0] _GEN_170 = opcode[6:2] == 5'h5 ? 64'h0 : _GEN_159; // @[ID_Stage.scala 149:58 ID_Stage.scala 94:33]
  wire [1:0] _GEN_171 = opcode[6:2] == 5'h5 ? 2'h0 : _GEN_160; // @[ID_Stage.scala 149:58 ID_Stage.scala 95:33]
  wire  _GEN_172 = opcode[6:2] == 5'h5 ? 1'h0 : _GEN_161; // @[ID_Stage.scala 149:58 ID_Stage.scala 96:33]
  wire [4:0] _GEN_173 = opcode[6:2] == 5'hd ? 5'h4 : _GEN_162; // @[ID_Stage.scala 139:56 ID_Stage.scala 140:41]
  wire [5:0] _GEN_174 = opcode[6:2] == 5'hd ? 6'h21 : _GEN_163; // @[ID_Stage.scala 139:56 ID_Stage.scala 141:41]
  wire [63:0] _GEN_176 = opcode[6:2] == 5'hd ? 64'hc : _GEN_165; // @[ID_Stage.scala 139:56 ID_Stage.scala 144:49]
  wire [4:0] _GEN_177 = opcode[6:2] == 5'hd ? rd : _GEN_166; // @[ID_Stage.scala 139:56 ID_Stage.scala 145:49]
  wire  _GEN_178 = opcode[6:2] == 5'hd | _GEN_167; // @[ID_Stage.scala 139:56 ID_Stage.scala 146:49]
  wire  _GEN_179 = opcode[6:2] == 5'hd ? 1'h0 : _GEN_168; // @[ID_Stage.scala 139:56 ID_Stage.scala 92:25]
  wire  _GEN_180 = opcode[6:2] == 5'hd ? 1'h0 : _GEN_169; // @[ID_Stage.scala 139:56 ID_Stage.scala 93:33]
  wire [63:0] _GEN_181 = opcode[6:2] == 5'hd ? 64'h0 : _GEN_170; // @[ID_Stage.scala 139:56 ID_Stage.scala 94:33]
  wire [1:0] _GEN_182 = opcode[6:2] == 5'hd ? 2'h0 : _GEN_171; // @[ID_Stage.scala 139:56 ID_Stage.scala 95:33]
  wire  _GEN_183 = opcode[6:2] == 5'hd ? 1'h0 : _GEN_172; // @[ID_Stage.scala 139:56 ID_Stage.scala 96:33]
  wire [4:0] _GEN_184 = opcode[6:2] == 5'h6 ? 5'h14 : _GEN_173; // @[ID_Stage.scala 122:55 ID_Stage.scala 123:41]
  wire [63:0] _GEN_186 = opcode[6:2] == 5'h6 ? _GEN_25 : _GEN_176; // @[ID_Stage.scala 122:55]
  wire [4:0] _GEN_187 = opcode[6:2] == 5'h6 ? rd : _GEN_177; // @[ID_Stage.scala 122:55 ID_Stage.scala 127:49]
  wire  _GEN_188 = opcode[6:2] == 5'h6 | _GEN_178; // @[ID_Stage.scala 122:55 ID_Stage.scala 128:49]
  wire [5:0] _GEN_189 = opcode[6:2] == 5'h6 ? _GEN_24 : _GEN_174; // @[ID_Stage.scala 122:55]
  wire  _GEN_190 = opcode[6:2] == 5'h6 ? 1'h0 : _GEN_179; // @[ID_Stage.scala 122:55 ID_Stage.scala 92:25]
  wire  _GEN_191 = opcode[6:2] == 5'h6 ? 1'h0 : _GEN_180; // @[ID_Stage.scala 122:55 ID_Stage.scala 93:33]
  wire [63:0] _GEN_192 = opcode[6:2] == 5'h6 ? 64'h0 : _GEN_181; // @[ID_Stage.scala 122:55 ID_Stage.scala 94:33]
  wire [1:0] _GEN_193 = opcode[6:2] == 5'h6 ? 2'h0 : _GEN_182; // @[ID_Stage.scala 122:55 ID_Stage.scala 95:33]
  wire  _GEN_194 = opcode[6:2] == 5'h6 ? 1'h0 : _GEN_183; // @[ID_Stage.scala 122:55 ID_Stage.scala 96:33]
  wire [4:0] _GEN_195 = opcode[6:2] == 5'h4 ? 5'h14 : _GEN_184; // @[ID_Stage.scala 101:42 ID_Stage.scala 102:38]
  wire [4:0] _GEN_197 = opcode[6:2] == 5'h4 ? rd : _GEN_187; // @[ID_Stage.scala 101:42 ID_Stage.scala 105:49]
  wire  _GEN_198 = opcode[6:2] == 5'h4 | _GEN_188; // @[ID_Stage.scala 101:42 ID_Stage.scala 106:49]
  wire [5:0] _GEN_199 = opcode[6:2] == 5'h4 ? {{1'd0}, _GEN_16} : _GEN_189; // @[ID_Stage.scala 101:42]
  wire [63:0] _GEN_200 = opcode[6:2] == 5'h4 ? _GEN_17 : _GEN_186; // @[ID_Stage.scala 101:42]
  wire  _GEN_201 = opcode[6:2] == 5'h4 ? 1'h0 : _GEN_190; // @[ID_Stage.scala 101:42 ID_Stage.scala 92:25]
  wire  _GEN_202 = opcode[6:2] == 5'h4 ? 1'h0 : _GEN_191; // @[ID_Stage.scala 101:42 ID_Stage.scala 93:33]
  wire [63:0] _GEN_203 = opcode[6:2] == 5'h4 ? 64'h0 : _GEN_192; // @[ID_Stage.scala 101:42 ID_Stage.scala 94:33]
  wire [1:0] _GEN_204 = opcode[6:2] == 5'h4 ? 2'h0 : _GEN_193; // @[ID_Stage.scala 101:42 ID_Stage.scala 95:33]
  wire  _GEN_205 = opcode[6:2] == 5'h4 ? 1'h0 : _GEN_194; // @[ID_Stage.scala 101:42 ID_Stage.scala 96:33]
  wire [4:0] _io_rs1_r_addr_T_2 = io_inst_type[4] ? rs1 : 5'h0; // @[ID_Stage.scala 304:39]
  wire [4:0] _io_rs2_r_addr_T_2 = io_inst_type[3] ? rs2 : 5'h0; // @[ID_Stage.scala 307:39]
  wire [5:0] _GEN_207 = reset ? 6'h0 : _GEN_199; // @[ID_Stage.scala 52:24 ID_Stage.scala 54:25]
  wire  w_ena_mul = reset ? 1'h0 : _GEN_198; // @[ID_Stage.scala 52:24 ID_Stage.scala 80:41]
  wire [4:0] w_addr_mul = reset ? 5'h0 : _GEN_197; // @[ID_Stage.scala 52:24 ID_Stage.scala 79:41]
  wire [63:0] op2_mul = reset ? 64'h0 : _GEN_200; // @[ID_Stage.scala 52:24 ID_Stage.scala 77:41]
  assign io_rs1_r_ena = reset ? 1'h0 : io_inst_type[4]; // @[ID_Stage.scala 52:24 ID_Stage.scala 56:25 ID_Stage.scala 303:25]
  assign io_rs1_r_addr = reset ? 5'h0 : _io_rs1_r_addr_T_2; // @[ID_Stage.scala 52:24 ID_Stage.scala 57:25 ID_Stage.scala 304:33]
  assign io_rs2_r_ena = reset ? 1'h0 : io_inst_type[3]; // @[ID_Stage.scala 52:24 ID_Stage.scala 59:25 ID_Stage.scala 306:25]
  assign io_rs2_r_addr = reset ? 5'h0 : _io_rs2_r_addr_T_2; // @[ID_Stage.scala 52:24 ID_Stage.scala 60:25 ID_Stage.scala 307:33]
  assign io_rd_w_ena = reset ? 1'h0 : w_ena_mul; // @[ID_Stage.scala 52:24 ID_Stage.scala 62:25 ID_Stage.scala 312:33]
  assign io_rd_w_addr = reset ? 5'h0 : w_addr_mul; // @[ID_Stage.scala 52:24 ID_Stage.scala 63:25 ID_Stage.scala 311:33]
  assign io_inst_type = reset ? 5'h0 : _GEN_195; // @[ID_Stage.scala 52:24 ID_Stage.scala 53:25]
  assign io_inst_opcode = {{2'd0}, _GEN_207}; // @[ID_Stage.scala 52:24 ID_Stage.scala 54:25]
  assign io_op1 = reset ? 64'h0 : op1_mul; // @[ID_Stage.scala 52:24 ID_Stage.scala 65:25 ID_Stage.scala 309:41]
  assign io_op2 = reset ? 64'h0 : op2_mul; // @[ID_Stage.scala 52:24 ID_Stage.scala 66:25 ID_Stage.scala 310:41]
  assign io_pc_ena_j = reset ? 1'h0 : _GEN_201; // @[ID_Stage.scala 52:24 ID_Stage.scala 68:25]
  assign io_pc_ena_b = reset ? 1'h0 : _GEN_202; // @[ID_Stage.scala 52:24 ID_Stage.scala 69:41]
  assign io_offset = reset ? 64'h0 : _GEN_203; // @[ID_Stage.scala 52:24 ID_Stage.scala 70:41]
  assign io_mem_sel = reset ? 2'h0 : _GEN_204; // @[ID_Stage.scala 52:24 ID_Stage.scala 72:41]
  assign io_mem_ext = reset ? 1'h0 : _GEN_205; // @[ID_Stage.scala 52:24 ID_Stage.scala 73:41]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_2 & ~_T_14 & ~_T_21 & ~_T_23 & ~_T_25 & ~_T_39 & ~_T_48 & ~_T_50 & ~_T_52 & ~_T_60 & ~_T_69 &
          _T_75 & ~reset) begin
          $fwrite(32'h80000002,"%b ",op1_mul[7:0]); // @[ID_Stage.scala 289:31]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module Exe_Stage(
  input         reset,
  input  [7:0]  io_inst_opcode,
  input  [63:0] io_op1,
  input  [63:0] io_op2,
  output [63:0] io_rd_data
);
  wire [63:0] _alu_result_T_1 = io_op1 + io_op2; // @[Exe_Stage.scala 25:76]
  wire [126:0] _GEN_21 = {{63'd0}, io_op1}; // @[Exe_Stage.scala 26:76]
  wire [126:0] _alu_result_T_3 = _GEN_21 << io_op2[5:0]; // @[Exe_Stage.scala 26:76]
  wire [63:0] _alu_result_T_4 = io_op1; // @[Exe_Stage.scala 27:77]
  wire [63:0] _alu_result_T_7 = $signed(io_op1) >>> io_op2[5:0]; // @[Exe_Stage.scala 27:100]
  wire [63:0] _alu_result_T_9 = io_op1 >> io_op2[5:0]; // @[Exe_Stage.scala 28:76]
  wire [63:0] _alu_result_T_11 = io_op2; // @[Exe_Stage.scala 29:97]
  wire [63:0] _alu_result_T_16 = io_op1 & io_op2; // @[Exe_Stage.scala 31:76]
  wire [63:0] _alu_result_T_17 = io_op1 | io_op2; // @[Exe_Stage.scala 32:76]
  wire [63:0] _alu_result_T_18 = io_op1 ^ io_op2; // @[Exe_Stage.scala 33:76]
  wire [63:0] _alu_result_T_20 = io_op1 - io_op2; // @[Exe_Stage.scala 34:76]
  wire [31:0] _alu_result_T_32 = io_op1[31:0] + io_op2[31:0]; // @[Exe_Stage.scala 40:111]
  wire [7:0] alu_result_lo_lo = {_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],
    _alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31]}; // @[Exe_Stage.scala 40:134]
  wire [15:0] alu_result_lo = {_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],
    _alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],alu_result_lo_lo}; // @[Exe_Stage.scala 40:134]
  wire [31:0] alu_result_hi_1 = {_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],
    _alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],_alu_result_T_32[31],alu_result_lo_lo,alu_result_lo}; // @[Exe_Stage.scala 40:134]
  wire [63:0] _alu_result_T_193 = {alu_result_hi_1,_alu_result_T_32}; // @[Cat.scala 30:58]
  wire [31:0] _alu_result_T_197 = io_op1[31:0] - io_op2[31:0]; // @[Exe_Stage.scala 41:111]
  wire [7:0] alu_result_lo_lo_1 = {_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[
    31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31]}; // @[Exe_Stage.scala 41:134]
  wire [15:0] alu_result_lo_2 = {_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31]
    ,_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],alu_result_lo_lo_1}; // @[Exe_Stage.scala 41:134]
  wire [31:0] alu_result_hi_3 = {_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31]
    ,_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],_alu_result_T_197[31],alu_result_lo_lo_1,
    alu_result_lo_2}; // @[Exe_Stage.scala 41:134]
  wire [63:0] _alu_result_T_358 = {alu_result_hi_3,_alu_result_T_197}; // @[Cat.scala 30:58]
  wire [62:0] _GEN_22 = {{31'd0}, io_op1[31:0]}; // @[Exe_Stage.scala 42:111]
  wire [62:0] _alu_result_T_361 = _GEN_22 << io_op2[4:0]; // @[Exe_Stage.scala 42:111]
  wire [7:0] alu_result_lo_lo_2 = {_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[
    31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31]}; // @[Exe_Stage.scala 42:134]
  wire [15:0] alu_result_lo_4 = {_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31]
    ,_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],alu_result_lo_lo_2}; // @[Exe_Stage.scala 42:134]
  wire [31:0] alu_result_hi_5 = {_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31]
    ,_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],_alu_result_T_361[31],alu_result_lo_lo_2,
    alu_result_lo_4}; // @[Exe_Stage.scala 42:134]
  wire [31:0] alu_result_lo_5 = _alu_result_T_361[31:0]; // @[Exe_Stage.scala 42:182]
  wire [63:0] _alu_result_T_490 = {alu_result_hi_5,alu_result_lo_5}; // @[Cat.scala 30:58]
  wire [31:0] _alu_result_T_492 = io_op1[31:0]; // @[Exe_Stage.scala 43:111]
  wire [31:0] _alu_result_T_494 = $signed(_alu_result_T_492) >>> io_op2[4:0]; // @[Exe_Stage.scala 43:118]
  wire [7:0] alu_result_lo_lo_3 = {_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[
    31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31]}; // @[Exe_Stage.scala 43:141]
  wire [15:0] alu_result_lo_6 = {_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31]
    ,_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],alu_result_lo_lo_3}; // @[Exe_Stage.scala 43:141]
  wire [31:0] alu_result_hi_7 = {_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31]
    ,_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],_alu_result_T_494[31],alu_result_lo_lo_3,
    alu_result_lo_6}; // @[Exe_Stage.scala 43:141]
  wire [31:0] alu_result_lo_7 = $signed(_alu_result_T_492) >>> io_op2[4:0]; // @[Exe_Stage.scala 43:189]
  wire [63:0] _alu_result_T_655 = {alu_result_hi_7,alu_result_lo_7}; // @[Cat.scala 30:58]
  wire [31:0] _alu_result_T_658 = io_op1[31:0] >> io_op2[4:0]; // @[Exe_Stage.scala 44:111]
  wire [7:0] alu_result_lo_lo_4 = {_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[
    31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31]}; // @[Exe_Stage.scala 44:134]
  wire [15:0] alu_result_lo_8 = {_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31]
    ,_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],alu_result_lo_lo_4}; // @[Exe_Stage.scala 44:134]
  wire [31:0] alu_result_hi_9 = {_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31]
    ,_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],_alu_result_T_658[31],alu_result_lo_lo_4,
    alu_result_lo_8}; // @[Exe_Stage.scala 44:134]
  wire [63:0] _alu_result_T_787 = {alu_result_hi_9,_alu_result_T_658}; // @[Cat.scala 30:58]
  wire [63:0] _GEN_0 = io_inst_opcode == 8'h22 ? _alu_result_T_787 : 64'h0; // @[Exe_Stage.scala 44:53 Exe_Stage.scala 44:66 Exe_Stage.scala 47:66]
  wire [63:0] _GEN_1 = io_inst_opcode == 8'h23 ? _alu_result_T_655 : _GEN_0; // @[Exe_Stage.scala 43:53 Exe_Stage.scala 43:66]
  wire [63:0] _GEN_2 = io_inst_opcode == 8'h21 ? _alu_result_T_490 : _GEN_1; // @[Exe_Stage.scala 42:53 Exe_Stage.scala 42:66]
  wire [63:0] _GEN_3 = io_inst_opcode == 8'h20 ? _alu_result_T_358 : _GEN_2; // @[Exe_Stage.scala 41:53 Exe_Stage.scala 41:66]
  wire [63:0] _GEN_4 = io_inst_opcode == 8'h1f ? _alu_result_T_193 : _GEN_3; // @[Exe_Stage.scala 40:53 Exe_Stage.scala 40:66]
  wire [63:0] _GEN_5 = io_inst_opcode == 8'h1e ? {{63'd0}, io_op1 >= io_op2} : _GEN_4; // @[Exe_Stage.scala 38:53 Exe_Stage.scala 38:66]
  wire [63:0] _GEN_6 = io_inst_opcode == 8'h1d ? {{63'd0}, $signed(_alu_result_T_4) >= $signed(_alu_result_T_11)} :
    _GEN_5; // @[Exe_Stage.scala 37:53 Exe_Stage.scala 37:66]
  wire [63:0] _GEN_7 = io_inst_opcode == 8'h1c ? {{63'd0}, io_op1 != io_op2} : _GEN_6; // @[Exe_Stage.scala 36:53 Exe_Stage.scala 36:66]
  wire [63:0] _GEN_8 = io_inst_opcode == 8'h1b ? {{63'd0}, io_op1 == io_op2} : _GEN_7; // @[Exe_Stage.scala 35:53 Exe_Stage.scala 35:66]
  wire [63:0] _GEN_9 = io_inst_opcode == 8'h1a ? _alu_result_T_20 : _GEN_8; // @[Exe_Stage.scala 34:53 Exe_Stage.scala 34:66]
  wire [63:0] _GEN_10 = io_inst_opcode == 8'h19 ? _alu_result_T_18 : _GEN_9; // @[Exe_Stage.scala 33:53 Exe_Stage.scala 33:66]
  wire [63:0] _GEN_11 = io_inst_opcode == 8'h18 ? _alu_result_T_17 : _GEN_10; // @[Exe_Stage.scala 32:53 Exe_Stage.scala 32:66]
  wire [63:0] _GEN_12 = io_inst_opcode == 8'h17 ? _alu_result_T_16 : _GEN_11; // @[Exe_Stage.scala 31:53 Exe_Stage.scala 31:66]
  wire [63:0] _GEN_13 = io_inst_opcode == 8'h16 ? {{63'd0}, io_op1 < io_op2} : _GEN_12; // @[Exe_Stage.scala 30:53 Exe_Stage.scala 30:66]
  wire [63:0] _GEN_14 = io_inst_opcode == 8'h15 ? {{63'd0}, $signed(_alu_result_T_4) < $signed(_alu_result_T_11)} :
    _GEN_13; // @[Exe_Stage.scala 29:53 Exe_Stage.scala 29:66]
  wire [63:0] _GEN_15 = io_inst_opcode == 8'h14 ? _alu_result_T_9 : _GEN_14; // @[Exe_Stage.scala 28:53 Exe_Stage.scala 28:66]
  wire [63:0] _GEN_16 = io_inst_opcode == 8'h13 ? _alu_result_T_7 : _GEN_15; // @[Exe_Stage.scala 27:53 Exe_Stage.scala 27:66]
  wire [126:0] _GEN_17 = io_inst_opcode == 8'h12 ? _alu_result_T_3 : {{63'd0}, _GEN_16}; // @[Exe_Stage.scala 26:53 Exe_Stage.scala 26:66]
  wire [126:0] _GEN_18 = io_inst_opcode == 8'h11 ? {{63'd0}, _alu_result_T_1} : _GEN_17; // @[Exe_Stage.scala 25:53 Exe_Stage.scala 25:66]
  wire [126:0] _GEN_19 = reset ? 127'h0 : _GEN_18; // @[Exe_Stage.scala 21:23 Exe_Stage.scala 22:20]
  wire [63:0] alu_result = _GEN_19[63:0];
  assign io_rd_data = reset ? 64'h0 : alu_result; // @[Exe_Stage.scala 21:23 Exe_Stage.scala 23:20 Exe_Stage.scala 49:21]
endmodule
module Branch(
  input         reset,
  input  [63:0] io_pc_out,
  input         io_pc_ena_j,
  input         io_pc_ena_b,
  input  [63:0] io_rd_data_in,
  input  [63:0] io_offset,
  output [63:0] io_rd_data_out,
  output [63:0] io_pc_in,
  output        io_pc_ena
);
  wire [63:0] _io_rd_data_out_T_1 = io_pc_out + 64'h4; // @[Branch.scala 30:42]
  wire [63:0] _io_pc_in_T = io_rd_data_in & 64'hfffffffffffffffe; // @[Branch.scala 31:46]
  wire  _T_3 = io_rd_data_in == 64'h1; // @[Branch.scala 34:33]
  wire [63:0] _io_pc_in_T_2 = io_pc_out + io_offset; // @[Branch.scala 38:42]
  wire  _GEN_1 = io_pc_ena_b & _T_3; // @[Branch.scala 33:41 Branch.scala 41:29]
  wire [63:0] _GEN_3 = io_pc_ena_b ? _io_pc_in_T_2 : 64'h0; // @[Branch.scala 33:41 Branch.scala 38:29 Branch.scala 43:29]
  wire  _GEN_4 = io_pc_ena_j | _GEN_1; // @[Branch.scala 28:39 Branch.scala 29:29]
  wire [63:0] _GEN_5 = io_pc_ena_j ? _io_rd_data_out_T_1 : io_rd_data_in; // @[Branch.scala 28:39 Branch.scala 30:29]
  wire [63:0] _GEN_6 = io_pc_ena_j ? _io_pc_in_T : _GEN_3; // @[Branch.scala 28:39 Branch.scala 31:29]
  assign io_rd_data_out = reset ? 64'h0 : _GEN_5; // @[Branch.scala 22:23 Branch.scala 24:25]
  assign io_pc_in = reset ? 64'h0 : _GEN_6; // @[Branch.scala 22:23 Branch.scala 25:24]
  assign io_pc_ena = reset ? 1'h0 : _GEN_4; // @[Branch.scala 22:23 Branch.scala 23:25]
endmodule
module Mem_Stage(
  input         reset,
  input  [4:0]  io_inst_type,
  input  [63:0] io_rd_data,
  input  [63:0] io_save_data,
  input  [63:0] io_mem_r_data,
  input         io_mem_ext,
  input  [1:0]  io_mem_sel,
  output        io_mem_r_ena,
  output [63:0] io_mem_r_addr,
  output        io_mem_w_ena,
  output [63:0] io_mem_w_addr,
  output [63:0] io_mem_w_data,
  output [63:0] io_mem_w_mask,
  output [63:0] io_rd_w_data
);
  wire  _T_1 = io_mem_sel == 2'h3; // @[Mem_Stage.scala 48:31]
  wire  _T_2 = io_mem_sel == 2'h2; // @[Mem_Stage.scala 52:31]
  wire [63:0] _GEN_0 = io_rd_data[2] ? 64'hffffffff00000000 : 64'hffffffff; // @[Mem_Stage.scala 53:39 Mem_Stage.scala 54:26 Mem_Stage.scala 56:26]
  wire  _T_5 = io_mem_sel == 2'h1; // @[Mem_Stage.scala 60:31]
  wire  _T_7 = io_rd_data[2:1] == 2'h1; // @[Mem_Stage.scala 62:34]
  wire  _T_9 = io_rd_data[2:1] == 2'h2; // @[Mem_Stage.scala 65:39]
  wire  _T_11 = io_rd_data[2:1] == 2'h3; // @[Mem_Stage.scala 68:39]
  wire [63:0] _GEN_1 = io_rd_data[2:1] == 2'h3 ? 64'hffff000000000000 : 64'hffff; // @[Mem_Stage.scala 68:47 Mem_Stage.scala 69:26 Mem_Stage.scala 72:26]
  wire [63:0] _GEN_2 = io_rd_data[2:1] == 2'h2 ? 64'hffff00000000 : _GEN_1; // @[Mem_Stage.scala 65:47 Mem_Stage.scala 66:26]
  wire [63:0] _GEN_3 = io_rd_data[2:1] == 2'h1 ? 64'hffff0000 : _GEN_2; // @[Mem_Stage.scala 62:42 Mem_Stage.scala 63:26]
  wire  _T_13 = io_rd_data[2:0] == 3'h1; // @[Mem_Stage.scala 77:34]
  wire  _T_15 = io_rd_data[2:0] == 3'h2; // @[Mem_Stage.scala 80:39]
  wire  _T_17 = io_rd_data[2:0] == 3'h3; // @[Mem_Stage.scala 83:39]
  wire  _T_19 = io_rd_data[2:0] == 3'h4; // @[Mem_Stage.scala 86:39]
  wire  _T_21 = io_rd_data[2:0] == 3'h5; // @[Mem_Stage.scala 89:39]
  wire  _T_23 = io_rd_data[2:0] == 3'h6; // @[Mem_Stage.scala 92:39]
  wire  _T_25 = io_rd_data[2:0] == 3'h7; // @[Mem_Stage.scala 95:39]
  wire [63:0] _GEN_4 = io_rd_data[2:0] == 3'h7 ? 64'hff00000000000000 : 64'hff; // @[Mem_Stage.scala 95:47 Mem_Stage.scala 96:26 Mem_Stage.scala 99:27]
  wire [63:0] _GEN_5 = io_rd_data[2:0] == 3'h6 ? 64'hff000000000000 : _GEN_4; // @[Mem_Stage.scala 92:47 Mem_Stage.scala 93:26]
  wire [63:0] _GEN_6 = io_rd_data[2:0] == 3'h5 ? 64'hff0000000000 : _GEN_5; // @[Mem_Stage.scala 89:47 Mem_Stage.scala 90:26]
  wire [63:0] _GEN_7 = io_rd_data[2:0] == 3'h4 ? 64'hff00000000 : _GEN_6; // @[Mem_Stage.scala 86:47 Mem_Stage.scala 87:26]
  wire [63:0] _GEN_8 = io_rd_data[2:0] == 3'h3 ? 64'hff000000 : _GEN_7; // @[Mem_Stage.scala 83:47 Mem_Stage.scala 84:26]
  wire [63:0] _GEN_9 = io_rd_data[2:0] == 3'h2 ? 64'hff0000 : _GEN_8; // @[Mem_Stage.scala 80:47 Mem_Stage.scala 81:26]
  wire [63:0] _GEN_10 = io_rd_data[2:0] == 3'h1 ? 64'hff00 : _GEN_9; // @[Mem_Stage.scala 77:42 Mem_Stage.scala 78:26]
  wire [63:0] _GEN_11 = io_mem_sel == 2'h1 ? _GEN_3 : _GEN_10; // @[Mem_Stage.scala 60:41]
  wire [63:0] _GEN_12 = io_mem_sel == 2'h2 ? _GEN_0 : _GEN_11; // @[Mem_Stage.scala 52:41]
  wire [63:0] _GEN_13 = io_mem_sel == 2'h3 ? 64'hffffffffffffffff : _GEN_12; // @[Mem_Stage.scala 48:41 Mem_Stage.scala 49:22]
  wire [63:0] the_mask = reset ? 64'h0 : _GEN_13; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 41:25]
  wire [63:0] _the_data_mask_T = io_mem_r_data & the_mask; // @[Mem_Stage.scala 110:46]
  wire [63:0] _GEN_36 = io_inst_type[1] ? _the_data_mask_T : 64'h0; // @[Mem_Stage.scala 107:40 Mem_Stage.scala 110:29 Mem_Stage.scala 182:29]
  wire [63:0] the_data_mask = reset ? 64'h0 : _GEN_36; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 42:25]
  wire [63:0] _the_data_ext_T = {{32'd0}, the_data_mask[63:32]}; // @[Mem_Stage.scala 120:54]
  wire [63:0] _GEN_14 = io_rd_data[2] ? _the_data_ext_T : the_data_mask; // @[Mem_Stage.scala 119:43 Mem_Stage.scala 120:37 Mem_Stage.scala 122:37]
  wire [63:0] _the_data_ext_T_1 = {{16'd0}, the_data_mask[63:16]}; // @[Mem_Stage.scala 132:54]
  wire [63:0] _the_data_ext_T_3 = {{48'd0}, the_data_mask[63:48]}; // @[Mem_Stage.scala 138:54]
  wire [63:0] _GEN_16 = _T_11 ? _the_data_ext_T_3 : the_data_mask; // @[Mem_Stage.scala 137:51 Mem_Stage.scala 138:37 Mem_Stage.scala 141:37]
  wire [63:0] _GEN_17 = _T_9 ? _the_data_ext_T : _GEN_16; // @[Mem_Stage.scala 134:51 Mem_Stage.scala 135:37]
  wire [63:0] _GEN_18 = _T_7 ? _the_data_ext_T_1 : _GEN_17; // @[Mem_Stage.scala 131:46 Mem_Stage.scala 132:37]
  wire [63:0] _the_data_ext_T_4 = {{8'd0}, the_data_mask[63:8]}; // @[Mem_Stage.scala 150:54]
  wire [63:0] _the_data_ext_T_6 = {{24'd0}, the_data_mask[63:24]}; // @[Mem_Stage.scala 156:54]
  wire [63:0] _the_data_ext_T_8 = {{40'd0}, the_data_mask[63:40]}; // @[Mem_Stage.scala 162:54]
  wire [63:0] _the_data_ext_T_10 = {{56'd0}, the_data_mask[63:56]}; // @[Mem_Stage.scala 168:54]
  wire [63:0] _GEN_20 = _T_25 ? _the_data_ext_T_10 : the_data_mask; // @[Mem_Stage.scala 167:51 Mem_Stage.scala 168:37 Mem_Stage.scala 171:37]
  wire [63:0] _GEN_21 = _T_23 ? _the_data_ext_T_3 : _GEN_20; // @[Mem_Stage.scala 164:51 Mem_Stage.scala 165:37]
  wire [63:0] _GEN_22 = _T_21 ? _the_data_ext_T_8 : _GEN_21; // @[Mem_Stage.scala 161:51 Mem_Stage.scala 162:37]
  wire [63:0] _GEN_23 = _T_19 ? _the_data_ext_T : _GEN_22; // @[Mem_Stage.scala 158:51 Mem_Stage.scala 159:37]
  wire [63:0] _GEN_24 = _T_17 ? _the_data_ext_T_6 : _GEN_23; // @[Mem_Stage.scala 155:51 Mem_Stage.scala 156:37]
  wire [63:0] _GEN_25 = _T_15 ? _the_data_ext_T_1 : _GEN_24; // @[Mem_Stage.scala 152:51 Mem_Stage.scala 153:37]
  wire [63:0] _GEN_26 = _T_13 ? _the_data_ext_T_4 : _GEN_25; // @[Mem_Stage.scala 149:46 Mem_Stage.scala 150:37]
  wire [63:0] _GEN_28 = _T_5 ? _GEN_18 : _GEN_26; // @[Mem_Stage.scala 129:45]
  wire [63:0] _GEN_30 = _T_2 ? _GEN_14 : _GEN_28; // @[Mem_Stage.scala 118:45]
  wire [63:0] _GEN_32 = _T_1 ? the_data_mask : _GEN_30; // @[Mem_Stage.scala 113:45 Mem_Stage.scala 114:33]
  wire [63:0] _GEN_37 = io_inst_type[1] ? _GEN_32 : 64'h0; // @[Mem_Stage.scala 107:40 Mem_Stage.scala 183:29]
  wire [63:0] the_data_ext = reset ? 64'h0 : _GEN_37; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 43:25]
  wire [7:0] io_rd_w_data_lo_lo = {the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],
    the_data_ext[31],the_data_ext[31],the_data_ext[31]}; // @[Mem_Stage.scala 125:110]
  wire [15:0] io_rd_w_data_lo = {the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],
    the_data_ext[31],the_data_ext[31],the_data_ext[31],io_rd_w_data_lo_lo}; // @[Mem_Stage.scala 125:110]
  wire [31:0] io_rd_w_data_hi_1 = {the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],the_data_ext[31],
    the_data_ext[31],the_data_ext[31],the_data_ext[31],io_rd_w_data_lo_lo,io_rd_w_data_lo}; // @[Mem_Stage.scala 125:110]
  wire [31:0] io_rd_w_data_lo_1 = the_data_ext[31:0]; // @[Mem_Stage.scala 125:132]
  wire [63:0] _io_rd_w_data_T_32 = {io_rd_w_data_hi_1,io_rd_w_data_lo_1}; // @[Cat.scala 30:58]
  wire [63:0] _io_rd_w_data_T_33 = {32'h0,io_rd_w_data_lo_1}; // @[Cat.scala 30:58]
  wire [63:0] _GEN_15 = io_mem_ext ? _io_rd_w_data_T_32 : _io_rd_w_data_T_33; // @[Mem_Stage.scala 125:45 Mem_Stage.scala 125:60 Mem_Stage.scala 126:60]
  wire [5:0] io_rd_w_data_lo_lo_lo_2 = {the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext
    [15],the_data_ext[15]}; // @[Mem_Stage.scala 144:110]
  wire [11:0] io_rd_w_data_lo_lo_2 = {the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[
    15],the_data_ext[15],io_rd_w_data_lo_lo_lo_2}; // @[Mem_Stage.scala 144:110]
  wire [23:0] io_rd_w_data_lo_4 = {the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15],
    the_data_ext[15],io_rd_w_data_lo_lo_lo_2,io_rd_w_data_lo_lo_2}; // @[Mem_Stage.scala 144:110]
  wire [15:0] io_rd_w_data_lo_5 = the_data_ext[15:0]; // @[Mem_Stage.scala 144:132]
  wire [63:0] _io_rd_w_data_T_82 = {the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15],the_data_ext[15]
    ,the_data_ext[15],io_rd_w_data_lo_lo_lo_2,io_rd_w_data_lo_lo_2,io_rd_w_data_lo_4,io_rd_w_data_lo_5}; // @[Cat.scala 30:58]
  wire [63:0] _io_rd_w_data_T_83 = {48'h0,io_rd_w_data_lo_5}; // @[Cat.scala 30:58]
  wire [63:0] _GEN_19 = io_mem_ext ? _io_rd_w_data_T_82 : _io_rd_w_data_T_83; // @[Mem_Stage.scala 144:45 Mem_Stage.scala 144:60 Mem_Stage.scala 145:60]
  wire [6:0] io_rd_w_data_lo_lo_lo_4 = {the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],
    the_data_ext[7],the_data_ext[7]}; // @[Mem_Stage.scala 174:109]
  wire [13:0] io_rd_w_data_lo_lo_4 = {the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],
    the_data_ext[7],the_data_ext[7],io_rd_w_data_lo_lo_lo_4}; // @[Mem_Stage.scala 174:109]
  wire [27:0] io_rd_w_data_lo_8 = {the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],
    the_data_ext[7],the_data_ext[7],io_rd_w_data_lo_lo_lo_4,io_rd_w_data_lo_lo_4}; // @[Mem_Stage.scala 174:109]
  wire [55:0] io_rd_w_data_hi_9 = {the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],the_data_ext[7],
    the_data_ext[7],the_data_ext[7],io_rd_w_data_lo_lo_lo_4,io_rd_w_data_lo_lo_4,io_rd_w_data_lo_8}; // @[Mem_Stage.scala 174:109]
  wire [7:0] io_rd_w_data_lo_9 = the_data_ext[7:0]; // @[Mem_Stage.scala 174:132]
  wire [63:0] _io_rd_w_data_T_140 = {io_rd_w_data_hi_9,io_rd_w_data_lo_9}; // @[Cat.scala 30:58]
  wire [63:0] _io_rd_w_data_T_141 = {56'h0,io_rd_w_data_lo_9}; // @[Cat.scala 30:58]
  wire [63:0] _GEN_27 = io_mem_ext ? _io_rd_w_data_T_140 : _io_rd_w_data_T_141; // @[Mem_Stage.scala 174:45 Mem_Stage.scala 174:60 Mem_Stage.scala 175:60]
  wire [63:0] _GEN_29 = _T_5 ? _GEN_19 : _GEN_27; // @[Mem_Stage.scala 129:45]
  wire [63:0] _GEN_31 = _T_2 ? _GEN_15 : _GEN_29; // @[Mem_Stage.scala 118:45]
  wire [63:0] _GEN_33 = _T_1 ? the_data_ext : _GEN_31; // @[Mem_Stage.scala 113:45 Mem_Stage.scala 115:33]
  wire [63:0] _GEN_35 = io_inst_type[1] ? io_rd_data : 64'h0; // @[Mem_Stage.scala 107:40 Mem_Stage.scala 109:29 Mem_Stage.scala 180:29]
  wire [63:0] _GEN_38 = io_inst_type[1] ? _GEN_33 : io_rd_data; // @[Mem_Stage.scala 107:40 Mem_Stage.scala 181:29]
  wire [95:0] _GEN_78 = {io_save_data, 32'h0}; // @[Mem_Stage.scala 201:53]
  wire [126:0] _io_mem_w_data_T = {{31'd0}, _GEN_78}; // @[Mem_Stage.scala 201:53]
  wire [126:0] _GEN_39 = io_rd_data[2] ? _io_mem_w_data_T : {{63'd0}, io_save_data}; // @[Mem_Stage.scala 200:43 Mem_Stage.scala 201:37 Mem_Stage.scala 203:37]
  wire [79:0] _GEN_79 = {io_save_data, 16'h0}; // @[Mem_Stage.scala 211:53]
  wire [94:0] _io_mem_w_data_T_1 = {{15'd0}, _GEN_79}; // @[Mem_Stage.scala 211:53]
  wire [111:0] _GEN_81 = {io_save_data, 48'h0}; // @[Mem_Stage.scala 217:53]
  wire [126:0] _io_mem_w_data_T_3 = {{15'd0}, _GEN_81}; // @[Mem_Stage.scala 217:53]
  wire [126:0] _GEN_40 = _T_11 ? _io_mem_w_data_T_3 : {{63'd0}, io_save_data}; // @[Mem_Stage.scala 216:51 Mem_Stage.scala 217:37 Mem_Stage.scala 220:37]
  wire [126:0] _GEN_41 = _T_9 ? _io_mem_w_data_T : _GEN_40; // @[Mem_Stage.scala 213:51 Mem_Stage.scala 214:37]
  wire [126:0] _GEN_42 = _T_7 ? {{32'd0}, _io_mem_w_data_T_1} : _GEN_41; // @[Mem_Stage.scala 210:46 Mem_Stage.scala 211:37]
  wire [71:0] _GEN_82 = {io_save_data, 8'h0}; // @[Mem_Stage.scala 226:53]
  wire [78:0] _io_mem_w_data_T_4 = {{7'd0}, _GEN_82}; // @[Mem_Stage.scala 226:53]
  wire [87:0] _GEN_84 = {io_save_data, 24'h0}; // @[Mem_Stage.scala 232:53]
  wire [94:0] _io_mem_w_data_T_6 = {{7'd0}, _GEN_84}; // @[Mem_Stage.scala 232:53]
  wire [103:0] _GEN_86 = {io_save_data, 40'h0}; // @[Mem_Stage.scala 238:53]
  wire [126:0] _io_mem_w_data_T_8 = {{23'd0}, _GEN_86}; // @[Mem_Stage.scala 238:53]
  wire [119:0] _GEN_88 = {io_save_data, 56'h0}; // @[Mem_Stage.scala 244:53]
  wire [126:0] _io_mem_w_data_T_10 = {{7'd0}, _GEN_88}; // @[Mem_Stage.scala 244:53]
  wire [126:0] _GEN_43 = _T_25 ? _io_mem_w_data_T_10 : {{63'd0}, io_save_data}; // @[Mem_Stage.scala 243:51 Mem_Stage.scala 244:37 Mem_Stage.scala 247:37]
  wire [126:0] _GEN_44 = _T_23 ? _io_mem_w_data_T_3 : _GEN_43; // @[Mem_Stage.scala 240:51 Mem_Stage.scala 241:37]
  wire [126:0] _GEN_45 = _T_21 ? _io_mem_w_data_T_8 : _GEN_44; // @[Mem_Stage.scala 237:51 Mem_Stage.scala 238:37]
  wire [126:0] _GEN_46 = _T_19 ? _io_mem_w_data_T : _GEN_45; // @[Mem_Stage.scala 234:51 Mem_Stage.scala 235:37]
  wire [126:0] _GEN_47 = _T_17 ? {{32'd0}, _io_mem_w_data_T_6} : _GEN_46; // @[Mem_Stage.scala 231:51 Mem_Stage.scala 232:37]
  wire [126:0] _GEN_48 = _T_15 ? {{32'd0}, _io_mem_w_data_T_1} : _GEN_47; // @[Mem_Stage.scala 228:51 Mem_Stage.scala 229:37]
  wire [126:0] _GEN_49 = _T_13 ? {{48'd0}, _io_mem_w_data_T_4} : _GEN_48; // @[Mem_Stage.scala 225:46 Mem_Stage.scala 226:37]
  wire [126:0] _GEN_50 = _T_5 ? _GEN_42 : _GEN_49; // @[Mem_Stage.scala 208:45]
  wire [126:0] _GEN_51 = _T_2 ? _GEN_39 : _GEN_50; // @[Mem_Stage.scala 199:45]
  wire [126:0] _GEN_52 = _T_1 ? {{63'd0}, io_save_data} : _GEN_51; // @[Mem_Stage.scala 195:45 Mem_Stage.scala 196:33]
  wire [63:0] _GEN_54 = io_inst_type[0] ? io_rd_data : 64'h0; // @[Mem_Stage.scala 189:40 Mem_Stage.scala 191:29 Mem_Stage.scala 252:29]
  wire [63:0] _GEN_55 = io_inst_type[0] ? the_mask : 64'h0; // @[Mem_Stage.scala 189:40 Mem_Stage.scala 192:29 Mem_Stage.scala 254:29]
  wire [126:0] _GEN_56 = io_inst_type[0] ? _GEN_52 : 127'h0; // @[Mem_Stage.scala 189:40 Mem_Stage.scala 253:29]
  wire [126:0] _GEN_61 = reset ? 127'h0 : _GEN_56; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 38:25]
  assign io_mem_r_ena = reset ? 1'h0 : io_inst_type[1]; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 34:25]
  assign io_mem_r_addr = reset ? 64'h0 : _GEN_35; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 35:25]
  assign io_mem_w_ena = reset ? 1'h0 : io_inst_type[0]; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 36:25]
  assign io_mem_w_addr = reset ? 64'h0 : _GEN_54; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 37:25]
  assign io_mem_w_data = _GEN_61[63:0];
  assign io_mem_w_mask = reset ? 64'h0 : _GEN_55; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 39:25]
  assign io_rd_w_data = reset ? 64'h0 : _GEN_38; // @[Mem_Stage.scala 33:24 Mem_Stage.scala 40:25]
endmodule
module WB_Stage(
  input         reset,
  input         io_rd_w_ena,
  input  [4:0]  io_rd_w_addr,
  input  [63:0] io_rd_w_data,
  output        io_wb_w_ena,
  output [4:0]  io_wb_w_addr,
  output [63:0] io_wb_w_data
);
  assign io_wb_w_ena = reset ? 1'h0 : io_rd_w_ena; // @[WB_Stage.scala 20:23 WB_Stage.scala 21:25 WB_Stage.scala 25:25]
  assign io_wb_w_addr = reset ? 5'h0 : io_rd_w_addr; // @[WB_Stage.scala 20:23 WB_Stage.scala 22:25 WB_Stage.scala 26:25]
  assign io_wb_w_data = reset ? 64'h0 : io_rd_w_data; // @[WB_Stage.scala 20:23 WB_Stage.scala 23:25 WB_Stage.scala 27:25]
endmodule
module Regfile(
  input         clock,
  input         reset,
  input  [4:0]  io_w_addr,
  input  [63:0] io_w_data,
  input         io_w_ena,
  input  [4:0]  io_r_addr1,
  input         io_r_ena1,
  input  [4:0]  io_r_addr2,
  input         io_r_ena2,
  output [63:0] io_r_data1,
  output [63:0] io_r_data2
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [63:0] _RAND_8;
  reg [63:0] _RAND_9;
  reg [63:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [63:0] _RAND_13;
  reg [63:0] _RAND_14;
  reg [63:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [63:0] _RAND_18;
  reg [63:0] _RAND_19;
  reg [63:0] _RAND_20;
  reg [63:0] _RAND_21;
  reg [63:0] _RAND_22;
  reg [63:0] _RAND_23;
  reg [63:0] _RAND_24;
  reg [63:0] _RAND_25;
  reg [63:0] _RAND_26;
  reg [63:0] _RAND_27;
  reg [63:0] _RAND_28;
  reg [63:0] _RAND_29;
  reg [63:0] _RAND_30;
  reg [63:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] regs_0; // @[Regfile.scala 23:23]
  reg [63:0] regs_1; // @[Regfile.scala 23:23]
  reg [63:0] regs_2; // @[Regfile.scala 23:23]
  reg [63:0] regs_3; // @[Regfile.scala 23:23]
  reg [63:0] regs_4; // @[Regfile.scala 23:23]
  reg [63:0] regs_5; // @[Regfile.scala 23:23]
  reg [63:0] regs_6; // @[Regfile.scala 23:23]
  reg [63:0] regs_7; // @[Regfile.scala 23:23]
  reg [63:0] regs_8; // @[Regfile.scala 23:23]
  reg [63:0] regs_9; // @[Regfile.scala 23:23]
  reg [63:0] regs_10; // @[Regfile.scala 23:23]
  reg [63:0] regs_11; // @[Regfile.scala 23:23]
  reg [63:0] regs_12; // @[Regfile.scala 23:23]
  reg [63:0] regs_13; // @[Regfile.scala 23:23]
  reg [63:0] regs_14; // @[Regfile.scala 23:23]
  reg [63:0] regs_15; // @[Regfile.scala 23:23]
  reg [63:0] regs_16; // @[Regfile.scala 23:23]
  reg [63:0] regs_17; // @[Regfile.scala 23:23]
  reg [63:0] regs_18; // @[Regfile.scala 23:23]
  reg [63:0] regs_19; // @[Regfile.scala 23:23]
  reg [63:0] regs_20; // @[Regfile.scala 23:23]
  reg [63:0] regs_21; // @[Regfile.scala 23:23]
  reg [63:0] regs_22; // @[Regfile.scala 23:23]
  reg [63:0] regs_23; // @[Regfile.scala 23:23]
  reg [63:0] regs_24; // @[Regfile.scala 23:23]
  reg [63:0] regs_25; // @[Regfile.scala 23:23]
  reg [63:0] regs_26; // @[Regfile.scala 23:23]
  reg [63:0] regs_27; // @[Regfile.scala 23:23]
  reg [63:0] regs_28; // @[Regfile.scala 23:23]
  reg [63:0] regs_29; // @[Regfile.scala 23:23]
  reg [63:0] regs_30; // @[Regfile.scala 23:23]
  reg [63:0] regs_31; // @[Regfile.scala 23:23]
  wire [63:0] _GEN_97 = 5'h1 == io_r_addr1 ? regs_1 : regs_0; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_98 = 5'h2 == io_r_addr1 ? regs_2 : _GEN_97; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_99 = 5'h3 == io_r_addr1 ? regs_3 : _GEN_98; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_100 = 5'h4 == io_r_addr1 ? regs_4 : _GEN_99; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_101 = 5'h5 == io_r_addr1 ? regs_5 : _GEN_100; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_102 = 5'h6 == io_r_addr1 ? regs_6 : _GEN_101; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_103 = 5'h7 == io_r_addr1 ? regs_7 : _GEN_102; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_104 = 5'h8 == io_r_addr1 ? regs_8 : _GEN_103; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_105 = 5'h9 == io_r_addr1 ? regs_9 : _GEN_104; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_106 = 5'ha == io_r_addr1 ? regs_10 : _GEN_105; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_107 = 5'hb == io_r_addr1 ? regs_11 : _GEN_106; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_108 = 5'hc == io_r_addr1 ? regs_12 : _GEN_107; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_109 = 5'hd == io_r_addr1 ? regs_13 : _GEN_108; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_110 = 5'he == io_r_addr1 ? regs_14 : _GEN_109; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_111 = 5'hf == io_r_addr1 ? regs_15 : _GEN_110; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_112 = 5'h10 == io_r_addr1 ? regs_16 : _GEN_111; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_113 = 5'h11 == io_r_addr1 ? regs_17 : _GEN_112; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_114 = 5'h12 == io_r_addr1 ? regs_18 : _GEN_113; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_115 = 5'h13 == io_r_addr1 ? regs_19 : _GEN_114; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_116 = 5'h14 == io_r_addr1 ? regs_20 : _GEN_115; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_117 = 5'h15 == io_r_addr1 ? regs_21 : _GEN_116; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_118 = 5'h16 == io_r_addr1 ? regs_22 : _GEN_117; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_119 = 5'h17 == io_r_addr1 ? regs_23 : _GEN_118; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_120 = 5'h18 == io_r_addr1 ? regs_24 : _GEN_119; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_121 = 5'h19 == io_r_addr1 ? regs_25 : _GEN_120; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_122 = 5'h1a == io_r_addr1 ? regs_26 : _GEN_121; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_123 = 5'h1b == io_r_addr1 ? regs_27 : _GEN_122; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_124 = 5'h1c == io_r_addr1 ? regs_28 : _GEN_123; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_125 = 5'h1d == io_r_addr1 ? regs_29 : _GEN_124; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_126 = 5'h1e == io_r_addr1 ? regs_30 : _GEN_125; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_127 = 5'h1f == io_r_addr1 ? regs_31 : _GEN_126; // @[Regfile.scala 39:46 Regfile.scala 39:46]
  wire [63:0] _GEN_128 = io_r_ena1 ? _GEN_127 : 64'h0; // @[Regfile.scala 39:33 Regfile.scala 39:46 Regfile.scala 40:46]
  wire [63:0] _GEN_130 = 5'h1 == io_r_addr2 ? regs_1 : regs_0; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_131 = 5'h2 == io_r_addr2 ? regs_2 : _GEN_130; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_132 = 5'h3 == io_r_addr2 ? regs_3 : _GEN_131; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_133 = 5'h4 == io_r_addr2 ? regs_4 : _GEN_132; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_134 = 5'h5 == io_r_addr2 ? regs_5 : _GEN_133; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_135 = 5'h6 == io_r_addr2 ? regs_6 : _GEN_134; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_136 = 5'h7 == io_r_addr2 ? regs_7 : _GEN_135; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_137 = 5'h8 == io_r_addr2 ? regs_8 : _GEN_136; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_138 = 5'h9 == io_r_addr2 ? regs_9 : _GEN_137; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_139 = 5'ha == io_r_addr2 ? regs_10 : _GEN_138; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_140 = 5'hb == io_r_addr2 ? regs_11 : _GEN_139; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_141 = 5'hc == io_r_addr2 ? regs_12 : _GEN_140; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_142 = 5'hd == io_r_addr2 ? regs_13 : _GEN_141; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_143 = 5'he == io_r_addr2 ? regs_14 : _GEN_142; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_144 = 5'hf == io_r_addr2 ? regs_15 : _GEN_143; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_145 = 5'h10 == io_r_addr2 ? regs_16 : _GEN_144; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_146 = 5'h11 == io_r_addr2 ? regs_17 : _GEN_145; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_147 = 5'h12 == io_r_addr2 ? regs_18 : _GEN_146; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_148 = 5'h13 == io_r_addr2 ? regs_19 : _GEN_147; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_149 = 5'h14 == io_r_addr2 ? regs_20 : _GEN_148; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_150 = 5'h15 == io_r_addr2 ? regs_21 : _GEN_149; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_151 = 5'h16 == io_r_addr2 ? regs_22 : _GEN_150; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_152 = 5'h17 == io_r_addr2 ? regs_23 : _GEN_151; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_153 = 5'h18 == io_r_addr2 ? regs_24 : _GEN_152; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_154 = 5'h19 == io_r_addr2 ? regs_25 : _GEN_153; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_155 = 5'h1a == io_r_addr2 ? regs_26 : _GEN_154; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_156 = 5'h1b == io_r_addr2 ? regs_27 : _GEN_155; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_157 = 5'h1c == io_r_addr2 ? regs_28 : _GEN_156; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_158 = 5'h1d == io_r_addr2 ? regs_29 : _GEN_157; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_159 = 5'h1e == io_r_addr2 ? regs_30 : _GEN_158; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_160 = 5'h1f == io_r_addr2 ? regs_31 : _GEN_159; // @[Regfile.scala 42:46 Regfile.scala 42:46]
  wire [63:0] _GEN_161 = io_r_ena2 ? _GEN_160 : 64'h0; // @[Regfile.scala 42:33 Regfile.scala 42:46 Regfile.scala 43:46]
  assign io_r_data1 = reset ? 64'h0 : _GEN_128; // @[Regfile.scala 35:23 Regfile.scala 36:20]
  assign io_r_data2 = reset ? 64'h0 : _GEN_161; // @[Regfile.scala 35:23 Regfile.scala 37:20]
  always @(posedge clock) begin
    if (reset) begin // @[Regfile.scala 23:23]
      regs_0 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_0 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h0 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_0 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_1 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_1 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_1 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_2 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_2 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h2 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_2 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_3 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_3 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h3 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_3 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_4 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_4 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h4 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_4 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_5 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_5 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h5 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_5 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_6 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_6 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h6 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_6 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_7 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_7 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h7 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_7 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_8 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_8 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h8 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_8 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_9 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_9 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h9 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_9 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_10 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_10 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'ha == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_10 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_11 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_11 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'hb == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_11 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_12 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_12 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'hc == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_12 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_13 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_13 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'hd == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_13 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_14 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_14 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'he == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_14 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_15 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_15 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'hf == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_15 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_16 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_16 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h10 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_16 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_17 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_17 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h11 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_17 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_18 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_18 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h12 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_18 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_19 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_19 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h13 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_19 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_20 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_20 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h14 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_20 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_21 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_21 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h15 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_21 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_22 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_22 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h16 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_22 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_23 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_23 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h17 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_23 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_24 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_24 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h18 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_24 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_25 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_25 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h19 == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_25 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_26 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_26 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1a == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_26 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_27 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_27 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1b == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_27 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_28 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_28 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1c == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_28 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_29 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_29 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1d == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_29 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_30 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_30 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1e == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_30 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
    if (reset) begin // @[Regfile.scala 23:23]
      regs_31 <= 64'h0; // @[Regfile.scala 23:23]
    end else if (reset) begin // @[Regfile.scala 25:23]
      regs_31 <= 64'h0; // @[Regfile.scala 27:21]
    end else if (io_w_ena & io_w_addr != 5'h0) begin // @[Regfile.scala 30:55]
      if (5'h1f == io_w_addr) begin // @[Regfile.scala 31:29]
        regs_31 <= io_w_data; // @[Regfile.scala 31:29]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  regs_0 = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  regs_1 = _RAND_1[63:0];
  _RAND_2 = {2{`RANDOM}};
  regs_2 = _RAND_2[63:0];
  _RAND_3 = {2{`RANDOM}};
  regs_3 = _RAND_3[63:0];
  _RAND_4 = {2{`RANDOM}};
  regs_4 = _RAND_4[63:0];
  _RAND_5 = {2{`RANDOM}};
  regs_5 = _RAND_5[63:0];
  _RAND_6 = {2{`RANDOM}};
  regs_6 = _RAND_6[63:0];
  _RAND_7 = {2{`RANDOM}};
  regs_7 = _RAND_7[63:0];
  _RAND_8 = {2{`RANDOM}};
  regs_8 = _RAND_8[63:0];
  _RAND_9 = {2{`RANDOM}};
  regs_9 = _RAND_9[63:0];
  _RAND_10 = {2{`RANDOM}};
  regs_10 = _RAND_10[63:0];
  _RAND_11 = {2{`RANDOM}};
  regs_11 = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  regs_12 = _RAND_12[63:0];
  _RAND_13 = {2{`RANDOM}};
  regs_13 = _RAND_13[63:0];
  _RAND_14 = {2{`RANDOM}};
  regs_14 = _RAND_14[63:0];
  _RAND_15 = {2{`RANDOM}};
  regs_15 = _RAND_15[63:0];
  _RAND_16 = {2{`RANDOM}};
  regs_16 = _RAND_16[63:0];
  _RAND_17 = {2{`RANDOM}};
  regs_17 = _RAND_17[63:0];
  _RAND_18 = {2{`RANDOM}};
  regs_18 = _RAND_18[63:0];
  _RAND_19 = {2{`RANDOM}};
  regs_19 = _RAND_19[63:0];
  _RAND_20 = {2{`RANDOM}};
  regs_20 = _RAND_20[63:0];
  _RAND_21 = {2{`RANDOM}};
  regs_21 = _RAND_21[63:0];
  _RAND_22 = {2{`RANDOM}};
  regs_22 = _RAND_22[63:0];
  _RAND_23 = {2{`RANDOM}};
  regs_23 = _RAND_23[63:0];
  _RAND_24 = {2{`RANDOM}};
  regs_24 = _RAND_24[63:0];
  _RAND_25 = {2{`RANDOM}};
  regs_25 = _RAND_25[63:0];
  _RAND_26 = {2{`RANDOM}};
  regs_26 = _RAND_26[63:0];
  _RAND_27 = {2{`RANDOM}};
  regs_27 = _RAND_27[63:0];
  _RAND_28 = {2{`RANDOM}};
  regs_28 = _RAND_28[63:0];
  _RAND_29 = {2{`RANDOM}};
  regs_29 = _RAND_29[63:0];
  _RAND_30 = {2{`RANDOM}};
  regs_30 = _RAND_30[63:0];
  _RAND_31 = {2{`RANDOM}};
  regs_31 = _RAND_31[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RVcore(
  input         clock,
  input         reset,
  input  [31:0] io_inst,
  input  [63:0] io_mem_r_data,
  output [63:0] io_inst_addr,
  output        io_inst_ena,
  output        io_mem_r_ena,
  output [63:0] io_mem_r_addr,
  output        io_mem_w_ena,
  output [63:0] io_mem_w_addr,
  output [63:0] io_mem_w_data,
  output [63:0] io_mem_w_mask
);
  wire  M_IF_Stage_clock; // @[RVcore.scala 24:33]
  wire  M_IF_Stage_reset; // @[RVcore.scala 24:33]
  wire  M_IF_Stage_io_pc_ena; // @[RVcore.scala 24:33]
  wire [63:0] M_IF_Stage_io_pc_in; // @[RVcore.scala 24:33]
  wire [63:0] M_IF_Stage_io_pc_out; // @[RVcore.scala 24:33]
  wire [63:0] M_IF_Stage_io_inst_addr; // @[RVcore.scala 24:33]
  wire  M_IF_Stage_io_inst_ena; // @[RVcore.scala 24:33]
  wire  M_ID_Stage_clock; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_reset; // @[RVcore.scala 25:33]
  wire [31:0] M_ID_Stage_io_inst; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_rs1_data; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_rs2_data; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_pc_out; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_rs1_r_ena; // @[RVcore.scala 25:33]
  wire [4:0] M_ID_Stage_io_rs1_r_addr; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_rs2_r_ena; // @[RVcore.scala 25:33]
  wire [4:0] M_ID_Stage_io_rs2_r_addr; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_rd_w_ena; // @[RVcore.scala 25:33]
  wire [4:0] M_ID_Stage_io_rd_w_addr; // @[RVcore.scala 25:33]
  wire [4:0] M_ID_Stage_io_inst_type; // @[RVcore.scala 25:33]
  wire [7:0] M_ID_Stage_io_inst_opcode; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_op1; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_op2; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_pc_ena_j; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_pc_ena_b; // @[RVcore.scala 25:33]
  wire [63:0] M_ID_Stage_io_offset; // @[RVcore.scala 25:33]
  wire [1:0] M_ID_Stage_io_mem_sel; // @[RVcore.scala 25:33]
  wire  M_ID_Stage_io_mem_ext; // @[RVcore.scala 25:33]
  wire  M_Exe_Stage_reset; // @[RVcore.scala 26:33]
  wire [7:0] M_Exe_Stage_io_inst_opcode; // @[RVcore.scala 26:33]
  wire [63:0] M_Exe_Stage_io_op1; // @[RVcore.scala 26:33]
  wire [63:0] M_Exe_Stage_io_op2; // @[RVcore.scala 26:33]
  wire [63:0] M_Exe_Stage_io_rd_data; // @[RVcore.scala 26:33]
  wire  M_Branch_reset; // @[RVcore.scala 27:33]
  wire [63:0] M_Branch_io_pc_out; // @[RVcore.scala 27:33]
  wire  M_Branch_io_pc_ena_j; // @[RVcore.scala 27:33]
  wire  M_Branch_io_pc_ena_b; // @[RVcore.scala 27:33]
  wire [63:0] M_Branch_io_rd_data_in; // @[RVcore.scala 27:33]
  wire [63:0] M_Branch_io_offset; // @[RVcore.scala 27:33]
  wire [63:0] M_Branch_io_rd_data_out; // @[RVcore.scala 27:33]
  wire [63:0] M_Branch_io_pc_in; // @[RVcore.scala 27:33]
  wire  M_Branch_io_pc_ena; // @[RVcore.scala 27:33]
  wire  M_Mem_Stage_reset; // @[RVcore.scala 28:33]
  wire [4:0] M_Mem_Stage_io_inst_type; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_rd_data; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_save_data; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_mem_r_data; // @[RVcore.scala 28:33]
  wire  M_Mem_Stage_io_mem_ext; // @[RVcore.scala 28:33]
  wire [1:0] M_Mem_Stage_io_mem_sel; // @[RVcore.scala 28:33]
  wire  M_Mem_Stage_io_mem_r_ena; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_mem_r_addr; // @[RVcore.scala 28:33]
  wire  M_Mem_Stage_io_mem_w_ena; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_mem_w_addr; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_mem_w_data; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_mem_w_mask; // @[RVcore.scala 28:33]
  wire [63:0] M_Mem_Stage_io_rd_w_data; // @[RVcore.scala 28:33]
  wire  M_WB_Stage_reset; // @[RVcore.scala 29:33]
  wire  M_WB_Stage_io_rd_w_ena; // @[RVcore.scala 29:33]
  wire [4:0] M_WB_Stage_io_rd_w_addr; // @[RVcore.scala 29:33]
  wire [63:0] M_WB_Stage_io_rd_w_data; // @[RVcore.scala 29:33]
  wire  M_WB_Stage_io_wb_w_ena; // @[RVcore.scala 29:33]
  wire [4:0] M_WB_Stage_io_wb_w_addr; // @[RVcore.scala 29:33]
  wire [63:0] M_WB_Stage_io_wb_w_data; // @[RVcore.scala 29:33]
  wire  M_Regfile_clock; // @[RVcore.scala 30:33]
  wire  M_Regfile_reset; // @[RVcore.scala 30:33]
  wire [4:0] M_Regfile_io_w_addr; // @[RVcore.scala 30:33]
  wire [63:0] M_Regfile_io_w_data; // @[RVcore.scala 30:33]
  wire  M_Regfile_io_w_ena; // @[RVcore.scala 30:33]
  wire [4:0] M_Regfile_io_r_addr1; // @[RVcore.scala 30:33]
  wire  M_Regfile_io_r_ena1; // @[RVcore.scala 30:33]
  wire [4:0] M_Regfile_io_r_addr2; // @[RVcore.scala 30:33]
  wire  M_Regfile_io_r_ena2; // @[RVcore.scala 30:33]
  wire [63:0] M_Regfile_io_r_data1; // @[RVcore.scala 30:33]
  wire [63:0] M_Regfile_io_r_data2; // @[RVcore.scala 30:33]
  IF_Stage M_IF_Stage ( // @[RVcore.scala 24:33]
    .clock(M_IF_Stage_clock),
    .reset(M_IF_Stage_reset),
    .io_pc_ena(M_IF_Stage_io_pc_ena),
    .io_pc_in(M_IF_Stage_io_pc_in),
    .io_pc_out(M_IF_Stage_io_pc_out),
    .io_inst_addr(M_IF_Stage_io_inst_addr),
    .io_inst_ena(M_IF_Stage_io_inst_ena)
  );
  ID_Stage M_ID_Stage ( // @[RVcore.scala 25:33]
    .clock(M_ID_Stage_clock),
    .reset(M_ID_Stage_reset),
    .io_inst(M_ID_Stage_io_inst),
    .io_rs1_data(M_ID_Stage_io_rs1_data),
    .io_rs2_data(M_ID_Stage_io_rs2_data),
    .io_pc_out(M_ID_Stage_io_pc_out),
    .io_rs1_r_ena(M_ID_Stage_io_rs1_r_ena),
    .io_rs1_r_addr(M_ID_Stage_io_rs1_r_addr),
    .io_rs2_r_ena(M_ID_Stage_io_rs2_r_ena),
    .io_rs2_r_addr(M_ID_Stage_io_rs2_r_addr),
    .io_rd_w_ena(M_ID_Stage_io_rd_w_ena),
    .io_rd_w_addr(M_ID_Stage_io_rd_w_addr),
    .io_inst_type(M_ID_Stage_io_inst_type),
    .io_inst_opcode(M_ID_Stage_io_inst_opcode),
    .io_op1(M_ID_Stage_io_op1),
    .io_op2(M_ID_Stage_io_op2),
    .io_pc_ena_j(M_ID_Stage_io_pc_ena_j),
    .io_pc_ena_b(M_ID_Stage_io_pc_ena_b),
    .io_offset(M_ID_Stage_io_offset),
    .io_mem_sel(M_ID_Stage_io_mem_sel),
    .io_mem_ext(M_ID_Stage_io_mem_ext)
  );
  Exe_Stage M_Exe_Stage ( // @[RVcore.scala 26:33]
    .reset(M_Exe_Stage_reset),
    .io_inst_opcode(M_Exe_Stage_io_inst_opcode),
    .io_op1(M_Exe_Stage_io_op1),
    .io_op2(M_Exe_Stage_io_op2),
    .io_rd_data(M_Exe_Stage_io_rd_data)
  );
  Branch M_Branch ( // @[RVcore.scala 27:33]
    .reset(M_Branch_reset),
    .io_pc_out(M_Branch_io_pc_out),
    .io_pc_ena_j(M_Branch_io_pc_ena_j),
    .io_pc_ena_b(M_Branch_io_pc_ena_b),
    .io_rd_data_in(M_Branch_io_rd_data_in),
    .io_offset(M_Branch_io_offset),
    .io_rd_data_out(M_Branch_io_rd_data_out),
    .io_pc_in(M_Branch_io_pc_in),
    .io_pc_ena(M_Branch_io_pc_ena)
  );
  Mem_Stage M_Mem_Stage ( // @[RVcore.scala 28:33]
    .reset(M_Mem_Stage_reset),
    .io_inst_type(M_Mem_Stage_io_inst_type),
    .io_rd_data(M_Mem_Stage_io_rd_data),
    .io_save_data(M_Mem_Stage_io_save_data),
    .io_mem_r_data(M_Mem_Stage_io_mem_r_data),
    .io_mem_ext(M_Mem_Stage_io_mem_ext),
    .io_mem_sel(M_Mem_Stage_io_mem_sel),
    .io_mem_r_ena(M_Mem_Stage_io_mem_r_ena),
    .io_mem_r_addr(M_Mem_Stage_io_mem_r_addr),
    .io_mem_w_ena(M_Mem_Stage_io_mem_w_ena),
    .io_mem_w_addr(M_Mem_Stage_io_mem_w_addr),
    .io_mem_w_data(M_Mem_Stage_io_mem_w_data),
    .io_mem_w_mask(M_Mem_Stage_io_mem_w_mask),
    .io_rd_w_data(M_Mem_Stage_io_rd_w_data)
  );
  WB_Stage M_WB_Stage ( // @[RVcore.scala 29:33]
    .reset(M_WB_Stage_reset),
    .io_rd_w_ena(M_WB_Stage_io_rd_w_ena),
    .io_rd_w_addr(M_WB_Stage_io_rd_w_addr),
    .io_rd_w_data(M_WB_Stage_io_rd_w_data),
    .io_wb_w_ena(M_WB_Stage_io_wb_w_ena),
    .io_wb_w_addr(M_WB_Stage_io_wb_w_addr),
    .io_wb_w_data(M_WB_Stage_io_wb_w_data)
  );
  Regfile M_Regfile ( // @[RVcore.scala 30:33]
    .clock(M_Regfile_clock),
    .reset(M_Regfile_reset),
    .io_w_addr(M_Regfile_io_w_addr),
    .io_w_data(M_Regfile_io_w_data),
    .io_w_ena(M_Regfile_io_w_ena),
    .io_r_addr1(M_Regfile_io_r_addr1),
    .io_r_ena1(M_Regfile_io_r_ena1),
    .io_r_addr2(M_Regfile_io_r_addr2),
    .io_r_ena2(M_Regfile_io_r_ena2),
    .io_r_data1(M_Regfile_io_r_data1),
    .io_r_data2(M_Regfile_io_r_data2)
  );
  assign io_inst_addr = M_IF_Stage_io_inst_addr; // @[RVcore.scala 32:33]
  assign io_inst_ena = M_IF_Stage_io_inst_ena; // @[RVcore.scala 33:33]
  assign io_mem_r_ena = M_Mem_Stage_io_mem_r_ena; // @[RVcore.scala 35:33]
  assign io_mem_r_addr = M_Mem_Stage_io_mem_r_addr; // @[RVcore.scala 36:33]
  assign io_mem_w_ena = M_Mem_Stage_io_mem_w_ena; // @[RVcore.scala 37:33]
  assign io_mem_w_addr = M_Mem_Stage_io_mem_w_addr; // @[RVcore.scala 38:33]
  assign io_mem_w_data = M_Mem_Stage_io_mem_w_data; // @[RVcore.scala 39:33]
  assign io_mem_w_mask = M_Mem_Stage_io_mem_w_mask; // @[RVcore.scala 40:33]
  assign M_IF_Stage_clock = clock;
  assign M_IF_Stage_reset = reset;
  assign M_IF_Stage_io_pc_ena = M_Branch_io_pc_ena; // @[RVcore.scala 42:33]
  assign M_IF_Stage_io_pc_in = M_Branch_io_pc_in; // @[RVcore.scala 43:33]
  assign M_ID_Stage_clock = clock;
  assign M_ID_Stage_reset = reset;
  assign M_ID_Stage_io_inst = io_inst; // @[RVcore.scala 45:33]
  assign M_ID_Stage_io_rs1_data = M_Regfile_io_r_data1; // @[RVcore.scala 46:33]
  assign M_ID_Stage_io_rs2_data = M_Regfile_io_r_data2; // @[RVcore.scala 47:33]
  assign M_ID_Stage_io_pc_out = M_IF_Stage_io_pc_out; // @[RVcore.scala 48:33]
  assign M_Exe_Stage_reset = reset;
  assign M_Exe_Stage_io_inst_opcode = M_ID_Stage_io_inst_opcode; // @[RVcore.scala 51:33]
  assign M_Exe_Stage_io_op1 = M_ID_Stage_io_op1; // @[RVcore.scala 52:33]
  assign M_Exe_Stage_io_op2 = M_ID_Stage_io_op2; // @[RVcore.scala 53:33]
  assign M_Branch_reset = reset;
  assign M_Branch_io_pc_out = M_IF_Stage_io_pc_out; // @[RVcore.scala 55:33]
  assign M_Branch_io_pc_ena_j = M_ID_Stage_io_pc_ena_j; // @[RVcore.scala 56:33]
  assign M_Branch_io_pc_ena_b = M_ID_Stage_io_pc_ena_b; // @[RVcore.scala 57:33]
  assign M_Branch_io_rd_data_in = M_Exe_Stage_io_rd_data; // @[RVcore.scala 58:33]
  assign M_Branch_io_offset = M_ID_Stage_io_offset; // @[RVcore.scala 59:33]
  assign M_Mem_Stage_reset = reset;
  assign M_Mem_Stage_io_inst_type = M_ID_Stage_io_inst_type; // @[RVcore.scala 61:33]
  assign M_Mem_Stage_io_rd_data = M_Branch_io_rd_data_out; // @[RVcore.scala 62:33]
  assign M_Mem_Stage_io_save_data = M_ID_Stage_io_rs2_data; // @[RVcore.scala 63:33]
  assign M_Mem_Stage_io_mem_r_data = io_mem_r_data; // @[RVcore.scala 66:33]
  assign M_Mem_Stage_io_mem_ext = M_ID_Stage_io_mem_ext; // @[RVcore.scala 64:33]
  assign M_Mem_Stage_io_mem_sel = M_ID_Stage_io_mem_sel; // @[RVcore.scala 65:33]
  assign M_WB_Stage_reset = reset;
  assign M_WB_Stage_io_rd_w_ena = M_ID_Stage_io_rd_w_ena; // @[RVcore.scala 68:33]
  assign M_WB_Stage_io_rd_w_addr = M_ID_Stage_io_rd_w_addr; // @[RVcore.scala 69:33]
  assign M_WB_Stage_io_rd_w_data = M_Mem_Stage_io_rd_w_data; // @[RVcore.scala 70:33]
  assign M_Regfile_clock = clock;
  assign M_Regfile_reset = reset;
  assign M_Regfile_io_w_addr = M_WB_Stage_io_wb_w_addr; // @[RVcore.scala 73:33]
  assign M_Regfile_io_w_data = M_WB_Stage_io_wb_w_data; // @[RVcore.scala 74:33]
  assign M_Regfile_io_w_ena = M_WB_Stage_io_wb_w_ena; // @[RVcore.scala 72:33]
  assign M_Regfile_io_r_addr1 = M_ID_Stage_io_rs1_r_addr; // @[RVcore.scala 76:33]
  assign M_Regfile_io_r_ena1 = M_ID_Stage_io_rs1_r_ena; // @[RVcore.scala 77:33]
  assign M_Regfile_io_r_addr2 = M_ID_Stage_io_rs2_r_addr; // @[RVcore.scala 78:33]
  assign M_Regfile_io_r_ena2 = M_ID_Stage_io_rs2_r_ena; // @[RVcore.scala 79:33]
endmodule
module DualPortRAM(
  input         clock,
  input         io_mem_r_ena,
  input  [63:0] io_mem_r_addr,
  input         io_mem_w_ena,
  input  [63:0] io_mem_w_addr,
  input  [63:0] io_mem_w_data,
  input  [63:0] io_mem_w_mask,
  output [63:0] io_mem_r_data
);
`ifdef RANDOMIZE_MEM_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
  reg [63:0] Ram_Block [0:1023]; // @[Ram.scala 20:24]
  wire [63:0] Ram_Block_io_mem_r_data_MPORT_data; // @[Ram.scala 20:24]
  wire [9:0] Ram_Block_io_mem_r_data_MPORT_addr; // @[Ram.scala 20:24]
  wire [63:0] Ram_Block_MPORT_data; // @[Ram.scala 20:24]
  wire [9:0] Ram_Block_MPORT_addr; // @[Ram.scala 20:24]
  wire  Ram_Block_MPORT_mask; // @[Ram.scala 20:24]
  wire  Ram_Block_MPORT_en; // @[Ram.scala 20:24]
  wire  _T_2 = ~io_mem_w_ena; // @[Ram.scala 22:33]
  wire  _T_3 = io_mem_r_ena & ~io_mem_w_ena; // @[Ram.scala 22:30]
  wire  _T_7 = io_mem_w_ena & ~io_mem_r_ena; // @[Ram.scala 25:36]
  assign Ram_Block_io_mem_r_data_MPORT_addr = io_mem_r_addr[9:0];
  assign Ram_Block_io_mem_r_data_MPORT_data = Ram_Block[Ram_Block_io_mem_r_data_MPORT_addr]; // @[Ram.scala 20:24]
  assign Ram_Block_MPORT_data = io_mem_w_data & io_mem_w_mask;
  assign Ram_Block_MPORT_addr = io_mem_w_addr[9:0];
  assign Ram_Block_MPORT_mask = 1'h1;
  assign Ram_Block_MPORT_en = _T_3 ? 1'h0 : _T_7;
  assign io_mem_r_data = io_mem_r_ena & ~io_mem_w_ena ? Ram_Block_io_mem_r_data_MPORT_data : 64'h0; // @[Ram.scala 22:54 Ram.scala 23:25]
  always @(posedge clock) begin
    if(Ram_Block_MPORT_en & Ram_Block_MPORT_mask) begin
      Ram_Block[Ram_Block_MPORT_addr] <= Ram_Block_MPORT_data; // @[Ram.scala 20:24]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {2{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    Ram_Block[initvar] = _RAND_0[63:0];
`endif // RANDOMIZE_MEM_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module rvcpu(
  input         clock,
  input         reset,
  input  [31:0] io_inst,
  output [63:0] io_inst_addr,
  output        io_inst_ena,
  output [63:0] io_mem_r_data
);
  wire  M_RVcore_clock; // @[RVcpu.scala 19:33]
  wire  M_RVcore_reset; // @[RVcpu.scala 19:33]
  wire [31:0] M_RVcore_io_inst; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_mem_r_data; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_inst_addr; // @[RVcpu.scala 19:33]
  wire  M_RVcore_io_inst_ena; // @[RVcpu.scala 19:33]
  wire  M_RVcore_io_mem_r_ena; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_mem_r_addr; // @[RVcpu.scala 19:33]
  wire  M_RVcore_io_mem_w_ena; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_mem_w_addr; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_mem_w_data; // @[RVcpu.scala 19:33]
  wire [63:0] M_RVcore_io_mem_w_mask; // @[RVcpu.scala 19:33]
  wire  M_RAM_clock; // @[RVcpu.scala 20:33]
  wire  M_RAM_io_mem_r_ena; // @[RVcpu.scala 20:33]
  wire [63:0] M_RAM_io_mem_r_addr; // @[RVcpu.scala 20:33]
  wire  M_RAM_io_mem_w_ena; // @[RVcpu.scala 20:33]
  wire [63:0] M_RAM_io_mem_w_addr; // @[RVcpu.scala 20:33]
  wire [63:0] M_RAM_io_mem_w_data; // @[RVcpu.scala 20:33]
  wire [63:0] M_RAM_io_mem_w_mask; // @[RVcpu.scala 20:33]
  wire [63:0] M_RAM_io_mem_r_data; // @[RVcpu.scala 20:33]
  RVcore M_RVcore ( // @[RVcpu.scala 19:33]
    .clock(M_RVcore_clock),
    .reset(M_RVcore_reset),
    .io_inst(M_RVcore_io_inst),
    .io_mem_r_data(M_RVcore_io_mem_r_data),
    .io_inst_addr(M_RVcore_io_inst_addr),
    .io_inst_ena(M_RVcore_io_inst_ena),
    .io_mem_r_ena(M_RVcore_io_mem_r_ena),
    .io_mem_r_addr(M_RVcore_io_mem_r_addr),
    .io_mem_w_ena(M_RVcore_io_mem_w_ena),
    .io_mem_w_addr(M_RVcore_io_mem_w_addr),
    .io_mem_w_data(M_RVcore_io_mem_w_data),
    .io_mem_w_mask(M_RVcore_io_mem_w_mask)
  );
  DualPortRAM M_RAM ( // @[RVcpu.scala 20:33]
    .clock(M_RAM_clock),
    .io_mem_r_ena(M_RAM_io_mem_r_ena),
    .io_mem_r_addr(M_RAM_io_mem_r_addr),
    .io_mem_w_ena(M_RAM_io_mem_w_ena),
    .io_mem_w_addr(M_RAM_io_mem_w_addr),
    .io_mem_w_data(M_RAM_io_mem_w_data),
    .io_mem_w_mask(M_RAM_io_mem_w_mask),
    .io_mem_r_data(M_RAM_io_mem_r_data)
  );
  assign io_inst_addr = M_RVcore_io_inst_addr; // @[RVcpu.scala 22:33]
  assign io_inst_ena = M_RVcore_io_inst_ena; // @[RVcpu.scala 23:33]
  assign io_mem_r_data = M_RAM_io_mem_r_data; // @[RVcpu.scala 24:33]
  assign M_RVcore_clock = clock;
  assign M_RVcore_reset = reset;
  assign M_RVcore_io_inst = io_inst; // @[RVcpu.scala 26:33]
  assign M_RVcore_io_mem_r_data = M_RAM_io_mem_r_data; // @[RVcpu.scala 27:33]
  assign M_RAM_clock = clock;
  assign M_RAM_io_mem_r_ena = M_RVcore_io_mem_r_ena; // @[RVcpu.scala 29:33]
  assign M_RAM_io_mem_r_addr = M_RVcore_io_mem_r_addr; // @[RVcpu.scala 30:33]
  assign M_RAM_io_mem_w_ena = M_RVcore_io_mem_w_ena; // @[RVcpu.scala 31:33]
  assign M_RAM_io_mem_w_addr = M_RVcore_io_mem_w_addr; // @[RVcpu.scala 32:33]
  assign M_RAM_io_mem_w_data = M_RVcore_io_mem_w_data; // @[RVcpu.scala 33:33]
  assign M_RAM_io_mem_w_mask = M_RVcore_io_mem_w_mask; // @[RVcpu.scala 34:33]
endmodule
